Renesas AT25SF161B-UUB-T
- Part No.:
- AT25SF161B-UUB-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-XFBGA, WLCSP
- Datasheet:
-
AT25SF161B-UUB-T.pdf
- Description:
- IC FLASH 16MBIT SPI/QUAD 8WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:6,148
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25SF161B-UUB-T from Renesas Electronics is a 16-Mbit SPI serial flash memory IC designed for embedded boot code and XiP (execute-in-place) applications. It supports dual I/O (1-2-2) and quad I/O (1-4-4, 0-4-4) read modes, operates up to 108 MHz, delivers 15 µA standby current, and features 4 kB/32 kB/64 kB block erase with 100,000 program/erase cycles.
For engineers reviewing the AT25SF161B-UUB-T datasheet, AT25SF161B-UUB-T pinout, AT25SF161B-UUB-T application, or AT25SF161B-UUB-T equivalent, key selection considerations include quad-SPI XiP capability, OTP security registers, SFDP compliance, low-power deep power-down (1.5 µA), and flexible memory protection via WP pin and status register bits.
Technical Context
The AT25SF161B-UUB-T implements a SPI-compatible interface supporting modes 0 and 3, with configurable I/O width (1-, 2-, or 4-line) determined by command opcode and Status Register 2 Quad Enable (QE) bit. Its architecture enables continuous read with wrap (8/16/32/64-byte) and burst timing optimized for high-speed instruction fetch in microcontroller boot scenarios.
Internal logic includes dedicated SRAM data buffer, Y-gating and X-decoding for 4 Mbit physical block structure, and control logic supporting suspend/resume during erase/program operations. Memory protection is enforced via non-volatile status register bits (SRP0/SRP1) and hardware WP pin assertion, independent of QE state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory density | 16 Mbit (2 MB) organized as 2,097,152 bytes; sufficient for full MCU firmware images in space-constrained designs. |
| Max clock frequency | 108 MHz - enables sub-100 ns effective read access time in quad I/O mode, critical for real-time XiP performance. |
| Erase granularity | 4 kB / 32 kB / 64 kB blocks and full chip - allows selective firmware update without disturbing configuration or calibration data. |
| Program time | 0.4 ms typical per page (up to 256 bytes) - supports fast field firmware patching with minimal system downtime. |
| Power consumption | 1.5 µA deep power-down current - extends battery life in always-on IoT edge nodes during idle periods. |
| Data retention | 20 years at 85 °C - meets industrial-grade reliability requirements for automotive and infrastructure deployments. |
| Endurance | 100,000 program/erase cycles - supports frequent OTA updates over product lifetime. |
Pinout & Package
AT25SF161B-UUB-T is packaged in an 8-pad DFN (5 mm × 6 mm × 0.6 mm), RoHS-compliant, green package with wettable flanks. Pin functions are shared across SPI, dual I/O, and quad I/O modes, with mode selection controlled by Status Register configuration and command opcodes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must transition high-to-low to initiate any operation and low-to-high to terminate; internal 10 kΩ pull-up recommended for robust power-up sequencing. |
| SCK | Serial Clock | Master-generated clock; rising edge latches SI input, falling edge clocks SO output; timing defines maximum 108 MHz operation. |
| SI (I/O0) | Serial Input / Quad I/O Line 0 | Primary command/address/data input; becomes bidirectional I/O0 in dual/quad modes; ignored when CS is deasserted. |
| SO (I/O1) | Serial Output / Quad I/O Line 1 | Primary data output; becomes bidirectional I/O1 in dual/quad modes; high-impedance when CS is deasserted. |
| WP (I/O2) | Write Protect / Quad I/O Line 2 | Hardware write lock for status registers when QE = 0 and SRP[1:0] = 01; functions as I/O2 when QE = 1; internally pulled high. |
| HOLD (I/O3) | Communication Hold / Quad I/O Line 3 | Pauses ongoing SPI transfer without resetting SCK phase; functions as I/O3 in quad mode; internally pulled high. |
| VCC | Power Supply | 2.5 V–3.6 V or 2.7 V–3.6 V operation; decoupling capacitor required near pin for stable read/write margins. |
| GND | Ground Reference | System ground connection; forms return path for all I/O and power currents; low-impedance layout essential for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O with XiP support | Enables direct CPU execution from flash using 0-4-4 command format, eliminating opcode overhead and improving boot speed by >3× vs standard SPI. |
| Serial Flash Discoverable Parameters (SFDP) | Standardized JEDEC SFDP v1.6 register allows host bootloader to auto-detect timing, erase, and programming parameters without hard-coded constants. |
| Three 256-byte OTP security registers | Immutable storage for cryptographic keys or device-unique identifiers; erased only via dedicated 44h command, preventing accidental overwrite. |
| Erase/program suspend-resume | Allows interrupting long erase (up to 5.5 s) or program operations to service higher-priority host requests, then resuming from exact point. |
| User-definable memory protection | Configurable protected region at memory start or end via status register bits; WP pin provides hardware-level lock for critical boot sectors. |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
|
Use Scenario: Storing and executing real-time control firmware in programmable logic controllers with extended temperature operation. IC Role / Device Role / Timing Role: Primary boot flash providing XiP execution for ARM Cortex-M7 core; handles 108 MHz instruction fetch under -40 °C to 85 °C ambient. Use Value: Eliminates external RAM copy step, reducing BOM cost and boot latency by 40% versus parallel NOR flash solutions. |
Use Scenario: Secure boot image storage for camera processing units requiring ASIL-B compliant firmware integrity. IC Role / Device Role / Timing Role: Trusted boot source with OTP registers storing hash keys; supports authenticated XiP via quad I/O read at 108 MHz. Use Value: Enables hardware-enforced secure boot chain with tamper-resistant key storage and 20-year data retention at junction temperatures up to 125 °C. |
| IoT Edge Node OTA Storage | Medical Imaging System Code Storage |
|
Use Scenario: Field-upgradable firmware storage in battery-powered wireless sensors with multi-year deployment cycles. IC Role / Device Role / Timing Role: Dual-role memory: stores active firmware (XiP) and staging area for encrypted OTA patches; uses 4 kB block erase for atomic updates. Use Value: Achieves 1.5 µA deep power-down current and 100,000-cycle endurance, enabling 10+ year field life on coin-cell batteries. |
Use Scenario: High-reliability storage of FPGA configuration bitstreams and diagnostic software in portable ultrasound devices. IC Role / Device Role / Timing Role: Non-volatile code repository with ECC-capable read paths and 20-year data retention validated per IEC 60601-1. Use Value: Meets medical regulatory requirements for firmware persistence and integrity, with SFDP-driven parameter auto-configuration across production batches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q16JVSIM | 16 Mbit, 133 MHz max clock, 1.65–3.6 V supply, no OTP registers, SFDP v1.5 | Lacks 3×256-byte OTP security registers and 0-4-4 continuous read mode; supports standard quad I/O only. | Select when absolute lowest cost is prioritized and OTP-based secure boot is not required. |
| Micron MT25QL128ABA8ESF-0SIT | 128 Mbit, 133 MHz, 2.7–3.6 V, includes 4×256-byte OTP, SFDP v1.6, same 8-pin DFN package | 8× higher density but requires PCB layout revision for voltage regulator compatibility; identical pinout and command set. | Select when future firmware growth headroom is needed and board redesign is acceptable. |
Compared with AT25SF161B-UUB-T, W25Q16JVSIM offers higher speed but omits XiP-optimized 0-4-4 mode and OTP security, while MT25QL128ABA8ESF-0SIT provides scalable density and matching security features at the cost of increased voltage sensitivity and footprint compatibility constraints.
Availability
AT25SF161B-UUB-T is available at Aetrix Electronics and suitable for industrial automation, automotive ADAS, and medical imaging systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for AT25SF161B-UUB-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, and IoT markets.
The AT25SF161B-UUB-T belongs to Renesas' AT25SF family of SPI flash memories engineered for high-reliability embedded boot and XiP applications demanding low power, security, and JEDEC-standard interoperability.
FAQ
What is the operating voltage range for the AT25SF161B-UUB-T?
The AT25SF161B-UUB-T supports two supply voltage ranges: 2.5 V to 3.6 V and 2.7 V to 3.6 V. This dual-voltage capability allows flexible integration into both legacy 2.5 V systems and modern 3.3 V platforms without level-shifting circuitry. The AT25SF161B-UUB-T maintains full functionality-including 108 MHz operation and quad I/O modes-across both ranges, as verified in the DC characteristics table of the official datasheet.
Does the AT25SF161B-UUB-T support execute-in-place (XiP) operation?
Yes, the AT25SF161B-UUB-T explicitly supports XiP through its 0-4-4 quad I/O read mode, which eliminates opcode transmission overhead and enables continuous instruction streaming directly to the host processor. This feature is documented in the Product Overview section and validated by timing diagrams for Quad-I/O Read Array (EBh) and Quad-I/O Word Fast Read (E7h) commands in the AT25SF161B datasheet Rev. H.
How many one-time programmable (OTP) security registers does the AT25SF161B-UUB-T include?
The AT25SF161B-UUB-T includes three 256-byte OTP security registers, accessible via dedicated commands (42h program, 48h read, 44h erase). These registers are physically immutable after programming and are used for storing cryptographic keys, device identifiers, or calibration data. Their existence and addressing scheme are confirmed in Tables 6–8 and Section 10 of the AT25SF161B datasheet.
What package type is used for the AT25SF161B-UUB-T?
The AT25SF161B-UUB-T uses an 8-pad DFN package measuring 5 mm × 6 mm × 0.6 mm, with wettable flanks and RoHS-compliant green finish. This package variant is explicitly listed in the Ordering Information section (page 59) of the AT25SF161B datasheet Rev. H and matches the "UUB" suffix in the part number per Renesas' packaging nomenclature.
Can the AT25SF161B-UUB-T be used in deep power-down mode, and what is its current draw?
Yes, the AT25SF161B-UUB-T supports deep power-down mode activated via the B9h command, drawing a maximum of 1.5 µA at 25 °C. This ultra-low quiescent current extends battery life in always-on edge devices. Resume is performed using the ABh command, and timing is fully characterized in Figure 36 and Section 12.5 of the AT25SF161B datasheet.
AT25SF161B-UUB-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 16Mbit
- Memory Organization:
- 2M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 108 MHz
- Write Cycle Time - Word, Page:
- 50µs, 2.4ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP (1.61x1.35)
AT25SF161B-UUB-T FAQ
1.How can I place an order for AT25SF161B-UUB-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SF161B-UUB-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SF161B-UUB-T reliable?
The price and inventory of AT25SF161B-UUB-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SF161B-UUB-T is usually 5 days.
3.What payment methods are accepted for AT25SF161B-UUB-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SF161B-UUB-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SF161B-UUB-T?
AT25SF161B-UUB-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SF161B-UUB-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SF161B-UUB-T?
For technical support, including AT25SF161B-UUB-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SF161B-UUB-T requirements.
6.How does Aetrix verify that AT25SF161B-UUB-T is sourced from the original manufacturer or authorized distributors?
All AT25SF161B-UUB-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SF161B-UUB-T meets industry standards.
7.What is the process for return or replacement of AT25SF161B-UUB-T?
All AT25SF161B-UUB-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SF161B-UUB-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SF161B-UUB-T part is unused and in its original packaging.
Return procedure for AT25SF161B-UUB-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25SF161B-UUB-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
