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Renesas AT25SF641-MHB-T

Name: AT25SF641-MHB-T
Brand: Renesas
SKU: AT25SF641-MHB-T
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT25SF641-MHB-T

Manufacturer:: Renesas

Category:: Memory

Package:: 8-UDFN Exposed Pad

Datasheet:: AT25SF641-MHB-T.pdf

Description:: IC FLASH 64MBIT SPI/QUAD 8UDFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

AT25SF641-MHB-T from Adesto Technologies (now part of Dialog Semiconductor) is a 64-Mbit SPI serial flash memory IC operating from 2.7 V to 3.6 V, supporting standard SPI, Dual I/O, Quad I/O, and QPI interfaces with up to 104 MHz clock frequency, 6 ns clock-to-output delay, and 52 MB/s continuous data transfer - deployed in code shadowing, XIP boot, and firmware storage for microcontroller-based embedded systems.

For engineers reviewing the AT25SF641-MHB-T datasheet, AT25SF641-MHB-T pinout, AT25SF641-MHB-T application, or AT25SF641-MHB-T equivalent, this page delivers verified electrical specs, validated pin functions, confirmed industrial temperature operation (–40°C to +85°C), JEDEC-compliant identification, and real-world erase/program timing metrics - all traceable to the official DS-25SF641–111G datasheet.

Technical Context

The AT25SF641-MHB-T implements a flexible multi-granularity erase architecture with 4 KB, 32 KB, 64 KB block erase and full chip erase, enabling efficient co-location of code and data segments without memory waste. Its dual- and quad-I/O modes repurpose SI/SO/WP/HOLD as bidirectional I/O0–I/O3 when the non-volatile Quad Enable (QE) bit is set.

It features hardware write protection via the WP pin (active-low), software/hardware-configurable block protection using BP2–BP0, TB, SEC, and CMP bits in two status registers, and a 4 Kbit secured one-time programmable (OTP) security register. Deep power-down current is 2 µA typical, supporting low-energy system states.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	64 Mbit (8 MB), organized as 65,536 × 256-byte pages - supports firmware images up to 8 MB without external expansion.
Supply Voltage	2.7 V to 3.6 V single supply - compatible with 3.3 V logic systems and tolerant of brown-out conditions down to 2.7 V.
Max Clock Frequency	104 MHz (SPI), enabling 208 MB/s dual-I/O and 416 MB/s quad-I/O burst reads - meets high-speed boot and XIP latency requirements.
Timing Performance	6 ns clock-to-output (tV1) and 0.6 ms typical page program time - reduces read latency and accelerates firmware updates.
Erase Flexibility	4 KB / 32 KB / 64 KB block erase (60 ms / 350 ms / 700 ms typical) plus full chip erase - allows selective field updates without full reflash.
Data Retention & Endurance	20 years retention; 100,000 program/erase cycles per block - qualified for long-life industrial and automotive control applications.
Operating Temperature	–40°C to +85°C industrial grade - validated for deployment in extended-temperature embedded controllers and IoT edge nodes.

Pinout & Package

AT25SF641-MHB-T is packaged in an 8-pad DFN (6 mm × 5 mm × 0.6 mm), RoHS-compliant, halide-free package with wettable flanks. Pin functions are electrically validated per DS-25SF641–111G Section 1.2 and Figure 1-2.

Pin/Terminal	Circuit Role	Design Meaning
CS	Chip Select	Active-low enable signal; places device in standby (high-Z outputs) when deasserted; required falling edge initiates instruction execution.
SCK	Serial Clock	Master-generated clock; latches SI on rising edge, clocks SO on falling edge; supports SPI Modes 0 and 3.
SI (I/O0)	Serial Input / Quad I/O Lane 0	Primary data-in during SPI; becomes bidirectional I/O0 in Dual/Quad/QPI modes - enables parallel data transfer on rising/falling edges.
SO (I/O1)	Serial Output / Quad I/O Lane 1	Primary data-out during SPI; becomes bidirectional I/O1 in Dual/Quad/QPI modes - doubles/quadruples throughput vs. standard SPI.
WP (I/O2)	Write Protect / Quad I/O Lane 2	Hardware lock for Status Register when QE = 0; becomes I/O2 in Quad/QPI modes - requires careful PCB routing if QE is enabled.
HOLD (I/O3)	Hold / Quad I/O Lane 3	Pauses ongoing SPI transaction without resetting state; becomes I/O3 in Quad/QPI modes - enables deterministic bus arbitration.
VCC	Power Supply	Single 2.7–3.6 V supply for all operations; powers internal charge pumps for erase/program - no auxiliary voltage required.
GND	Ground Reference	System ground return path; must be low-impedance and co-located with VCC decoupling to ensure stable core voltage during high-current erase cycles.

Key Features

Feature	Design Value
Quad Peripheral Interface (QPI)	Reduces instruction overhead by 4× vs. SPI: 2-clock instruction fetch (vs. 8-clock) improves XIP efficiency and reduces CPU wait states.
Erase/Program Suspend & Resume	Enables priority interrupt handling during long erase/program cycles - critical for real-time systems requiring deterministic response latency.
Serial Flash Discoverable Parameters (SFDP)	Standardized JEDEC SFDP register (5Ah) provides runtime-configurable timing, density, and feature flags - simplifies driver portability across flash vendors.
4 Kbit Secured OTP Security Register	Stores immutable keys, certificates, or calibration data - isolated from main array and protected by dedicated lock bits to prevent overwrite or readout.
Flexible Block Protection Scheme	Configurable top/bottom, sector/block, and complement-protection modes (via BP2–BP0, TB, SEC, CMP) enable fine-grained firmware partitioning and secure bootloader isolation.

Applications

Boot Code Storage	Firmware Over-the-Air (FOTA)
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers during cold start. IC Role / Device Role / Timing Role: Non-volatile code repository accessed via SPI/XIP; delivers first instructions within <100 µs of reset release. Use Value: 104 MHz QPI read speed and 6 ns tV1 enable sub-millisecond boot time; 4 KB erase granularity allows atomic bootloader updates without corrupting active firmware.	Use Scenario: Receiving and validating encrypted firmware patches in connected industrial gateways or smart meters. IC Role / Device Role / Timing Role: Secure, field-upgradable storage partitioned into active/inactive banks with hardware write protection. Use Value: 100,000-cycle endurance and 20-year retention guarantee multi-decade field life; OTP register stores root-of-trust keys for patch authentication.
Configuration & Calibration Data	Real-Time OS Kernel Image
Use Scenario: Persisting sensor calibration coefficients, network credentials, and user preferences in medical diagnostic equipment. IC Role / Device Role / Timing Role: Parameter store with byte-level write capability and hardware lock (WP pin) against accidental overwrites. Use Value: Page-program flexibility (1–256 bytes) minimizes write latency for small config changes; deep power-down (2 µA) extends battery life in portable devices.	Use Scenario: Hosting RTOS kernel image for deterministic execution directly from flash (XIP) in avionics or robotics controllers. IC Role / Device Role / Timing Role: Low-latency instruction source with dual/quad read support to sustain >30 MB/s sustained fetch bandwidth. Use Value: 52 MB/s continuous transfer rate eliminates instruction cache misses; suspend/resume avoids jitter during kernel update under real-time constraints.

Boot Code Storage

Firmware Over-the-Air (FOTA)

Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers during cold start.

IC Role / Device Role / Timing Role: Non-volatile code repository accessed via SPI/XIP; delivers first instructions within <100 µs of reset release.

Use Value: 104 MHz QPI read speed and 6 ns tV1 enable sub-millisecond boot time; 4 KB erase granularity allows atomic bootloader updates without corrupting active firmware.

Use Scenario: Receiving and validating encrypted firmware patches in connected industrial gateways or smart meters.

IC Role / Device Role / Timing Role: Secure, field-upgradable storage partitioned into active/inactive banks with hardware write protection.

Use Value: 100,000-cycle endurance and 20-year retention guarantee multi-decade field life; OTP register stores root-of-trust keys for patch authentication.

Configuration & Calibration Data

Real-Time OS Kernel Image

Use Scenario: Persisting sensor calibration coefficients, network credentials, and user preferences in medical diagnostic equipment.

IC Role / Device Role / Timing Role: Parameter store with byte-level write capability and hardware lock (WP pin) against accidental overwrites.

Use Value: Page-program flexibility (1–256 bytes) minimizes write latency for small config changes; deep power-down (2 µA) extends battery life in portable devices.

Use Scenario: Hosting RTOS kernel image for deterministic execution directly from flash (XIP) in avionics or robotics controllers.

IC Role / Device Role / Timing Role: Low-latency instruction source with dual/quad read support to sustain >30 MB/s sustained fetch bandwidth.

Use Value: 52 MB/s continuous transfer rate eliminates instruction cache misses; suspend/resume avoids jitter during kernel update under real-time constraints.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial flash memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT25SF641B-MHB-T	Direct revision upgrade: same pinout, enhanced reliability, improved ECC, and updated SFDP tables; replaces AT25SF641 per manufacturer notice.	Identical use cases but qualified for new designs; supports same instruction set and timing, with tighter AC parameter tolerances.	Select AT25SF641B-MHB-T for new designs - it is the recommended replacement with identical footprint and backward-compatible firmware.
Winbond W25Q64JVSSIQ	64 Mbit, 3.3 V, supports SPI/QPI/DTR; lacks OTP security register and has different status register layout and QE implementation.	Functional substitute for basic code storage, but requires driver adaptation for protection schemes and lacks secured key storage.	Choose W25Q64JVSSIQ only when OTP and advanced block protection are unnecessary and cross-vendor qualification is complete.

Compared with AT25SF641-MHB-T, the AT25SF641B-MHB-T offers improved process reliability and extended lifecycle support, while Winbond W25Q64JVSSIQ provides cost-optimized compatibility at the expense of security and protection configurability - making the B-revision the preferred drop-in upgrade and Winbond a secondary option requiring firmware validation.

Availability

AT25SF641-MHB-T is available at Aetrix Electronics and suitable for industrial control systems, medical diagnostics equipment, and automotive infotainment modules requiring stable component supply, long-term obsolescence management, and guaranteed traceability.

Supply support for AT25SF641-MHB-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies, acquired by Dialog Semiconductor in 2020, specialized in low-power, high-performance non-volatile memory and analog interface solutions for IoT and embedded markets.

The AT25SF641 product line was designed for resource-constrained embedded systems needing fast, secure, and configurable flash storage - emphasizing XIP performance, firmware integrity, and industrial-grade reliability.

FAQ

Is AT25SF641-MHB-T still recommended for new designs?

No - Dialog Semiconductor explicitly marks AT25SF641-MHB-T as "NOT RECOMMENDED FOR NEW DESIGNS" in the official datasheet (DS-25SF641–111G). The AT25SF641B-MHB-T is the designated replacement, offering identical pinout, enhanced reliability, and updated SFDP compliance. For new projects, engineers should migrate to the B-revision to ensure long-term supply and technical support.

What is the function of the HOLD pin on AT25SF641-MHB-T?

The HOLD pin on AT25SF641-MHB-T pauses ongoing SPI transactions without resetting internal state - allowing the host controller to service higher-priority interrupts and resume communication seamlessly. It operates only when CS is low and SCK is low at both entry and exit edges. In Quad I/O or QPI mode (QE=1), HOLD becomes I/O3 and loses its hold functionality.

Does AT25SF641-MHB-T support Quad SPI and QPI simultaneously?

No - AT25SF641-MHB-T supports Standard SPI, Dual I/O, Quad I/O, and QPI as mutually exclusive operational modes. The Enable QPI (38h) instruction switches from SPI modes to QPI mode, and the Disable QPI (FFh) instruction returns to SPI mode. Only one interface protocol is active at any time, and mode switching requires explicit software command.

How does the Quad Enable (QE) bit affect pin functionality on AT25SF641-MHB-T?

When the non-volatile Quad Enable (QE) bit in Status Register-2 is cleared (0), WP and HOLD retain their hardware protection functions. When QE is set (1), WP becomes I/O2 and HOLD becomes I/O3 - enabling four-lane data transfer. Warning: setting QE=1 while WP or HOLD are hard-wired to VCC/GND may cause bus contention or malfunction.

What erase block sizes does AT25SF641-MHB-T support, and why does it matter?

AT25SF641-MHB-T supports 4 KB, 32 KB, 64 KB block erase and full chip erase. This multi-level granularity prevents wasted space: small code modules or configuration data can occupy dedicated 4 KB blocks, avoiding the inefficiency of erasing large 64 KB regions just to update a few bytes - directly improving usable memory density and field-upgrade safety.

AT25SF641-MHB-T Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 8-UDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 64Mbit

Memory Organization:: 8M x 8

Memory Interface:: SPI - Quad I/O, QPI

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 150µs, 5ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-UDFN (5x6)

AT25SF641-MHB-T FAQ

1.How can I place an order for AT25SF641-MHB-T through Aetrix?

Please submit a Request for Quotation (RFQ) for AT25SF641-MHB-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT25SF641-MHB-T reliable?

The price and inventory of AT25SF641-MHB-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SF641-MHB-T is usually 5 days.

3.What payment methods are accepted for AT25SF641-MHB-T?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SF641-MHB-T transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT25SF641-MHB-T?

AT25SF641-MHB-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT25SF641-MHB-T order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT25SF641-MHB-T?

For technical support, including AT25SF641-MHB-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SF641-MHB-T requirements.

6.How does Aetrix verify that AT25SF641-MHB-T is sourced from the original manufacturer or authorized distributors?

All AT25SF641-MHB-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SF641-MHB-T meets industry standards.

7.What is the process for return or replacement of AT25SF641-MHB-T?

All AT25SF641-MHB-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SF641-MHB-T, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT25SF641-MHB-T part is unused and in its original packaging.

Return procedure for AT25SF641-MHB-T:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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