Renesas AT25SL128A-UIUE-T
- Part No.:
- AT25SL128A-UIUE-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 21-XFBGA, WLCSP
- Datasheet:
-
AT25SL128A-UIUE-T.pdf
- Description:
- IC FLASH 128MBIT SPI 21WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT25SL128A-UIUE-T from Renesas Electronics is a 128-Mbit SPI serial flash memory IC supporting Dual I/O, Quad I/O, and QPI interfaces with 1.7–2.0 V single-supply operation, 133 MHz fast read speed, and industrial temperature range (−40 °C to +85 °C). It enables Execute-in-Place (XiP) in embedded boot and firmware storage applications.
For engineers reviewing the AT25SL128A-UIUE-T datasheet, AT25SL128A-UIUE-T pinout, AT25SL128A-UIUE-T application, or AT25SL128A-UIUE-T equivalent, key selection criteria include quad/dual I/O timing compliance, 21-ball WLCSP package footprint, write suspend/resume capability, SFDP register support, and deep power-down current (2 µA typical).
Technical Context
The AT25SL128A-UIUE-T implements a flexible command-set architecture supporting SPI Modes 0/3, Dual SPI (1-1-2), Quad SPI (1-1-4), Quad I/O (1-4-4, 0-4-4), and QPI (4-4-4) protocols. Its memory array is organized into uniform 4-kB sectors with configurable block protection via status register bits BP2–BP0 and TB/SEC controls.
It integrates hardware-based write protection using the WP pin and SRP1/SRP0 bits, supports continuous read with 8/16/32/64-byte wrap, and provides erase/program suspend-resume functionality for real-time system responsiveness during background operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 Mbit (16 MB); sufficient for full firmware images and configuration data in space-constrained designs. |
| Supply Voltage | 1.7 V – 2.0 V; compatible with low-voltage SoCs and battery-powered systems requiring tight power rail control. |
| Max Read Speed | 133 MHz in QPI mode; enables high-bandwidth XiP execution without external cache bottlenecks. |
| Erase Time (4 kB) | 60 ms typical; allows rapid field updates of small firmware segments without long downtime. |
| Page Program Time | 0.6 ms typical; supports efficient incremental configuration writes in real-time logging or parameter storage. |
| Deep Power-Down Current | 2 µA typical; extends battery life in always-on IoT edge nodes during idle periods. |
| Data Retention | 20 years; ensures long-term reliability for industrial deployments without refresh cycles. |
| Endurance | 100,000 program/erase cycles; suitable for frequent OTA update scenarios in connected devices. |
Pinout & Package
AT25SL128A-UIUE-T uses a 21-ball low-profile WLCSP (UI package variant) measuring 3.0 × 2.5 × 0.5 mm, optimized for ultra-compact PCB layouts in wearables and sensor modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable for SPI/QPI command initiation; must be asserted before clock/data transitions. |
| SCK | Serial Clock | Master-generated clock synchronizing all SPI/QPI transfers; supports up to 133 MHz in QPI mode. |
| IO0 (SI) | Serial Input / Data In | Primary input for commands, addresses, and program data in standard SPI; bidirectional in Dual/Quad I/O modes. |
| IO1 (SO) | Serial Output / Data Out | Primary output for read data in SPI; becomes bidirectional in Dual/Quad I/O for address/command feedback. |
| IO2 (WP) | Write Protect Input | Hardware-level protection enable; asserts memory lock when pulled low, independent of status register settings. |
| IO3 (HOLD) | Hold Input | Pauses ongoing read/write operations without deselecting chip; preserves internal state during host arbitration. |
| VCC | Power Supply | 1.7–2.0 V core supply; requires local decoupling due to fast switching transients in QPI mode. |
| GND | Ground Reference | Common return path for all I/O and power; must be low-impedance to maintain signal integrity at 133 MHz. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O & QPI Support | Enables 4-bit-per-cycle data transfer (1-4-4, 4-4-4), doubling bandwidth over standard SPI for XiP latency reduction. |
| Erase/Program Suspend | Allows immediate pause/resume of background erase or program operations, enabling time-critical foreground tasks. |
| Serial Flash Discoverable Parameter (SFDP) | Provides standardized JEDEC-compliant register map for automatic host configuration without hardcoded timing tables. |
| User-Definable Memory Protection | Configurable protected zones at memory start/end via BP/TB bits, preventing accidental overwrite of bootloader or calibration data. |
| Continuous Read with Wrap | Eliminates repeated command opcodes during burst reads, reducing bus overhead and improving throughput in streaming applications. |
| Deep Power-Down Mode | Reduces current to 2 µA while preserving memory contents, ideal for energy harvesting or battery-backed standby states. |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing firmware and configuration parameters in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile program memory providing reliable boot code and runtime parameter storage with 20-year data retention. Use Value: Industrial temperature rating (−40 °C to +85 °C) and 100,000 endurance cycles ensure stable operation across thermal cycling and frequent field updates. | Use Scenario: Hosting boot firmware and sensor calibration data for camera/radar modules in advanced driver-assistance systems. IC Role / Device Role / Timing Role: High-speed XiP-capable flash enabling direct code execution from memory to reduce boot latency and external RAM dependency. Use Value: 133 MHz QPI read speed and continuous read with wrap minimize instruction fetch delays critical for real-time processing pipelines. |
| IoT Edge Node Configuration | Medical Wearable Data Logger |
Use Scenario: Storing device-specific credentials, network profiles, and OTA update staging buffers in battery-powered smart sensors. IC Role / Device Role / Timing Role: Secure, low-power nonvolatile storage supporting encrypted parameter writes and protected OTP regions. Use Value: 2 µA deep power-down current extends multi-year battery life, while WP pin hardware lock prevents remote firmware corruption. | Use Scenario: Capturing physiological sensor readings and event logs in compact wearable health monitors with strict size constraints. IC Role / Device Role / Timing Role: Ultra-small-footprint (3.0 × 2.5 mm) WLCSP flash providing persistent storage for time-stamped biometric data. Use Value: 21-ball UI package enables PCB area savings >60% vs. SOIC, while 4-kB sector erase allows efficient log rotation without full-chip erasure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q128JVSIM | 3.3 V supply (vs. 1.7–2.0 V); same 128-Mbit density, QPI, and WLCSP package; no deep power-down mode (5 µA vs. 2 µA). | Requires 3.3 V rail; less suitable for ultra-low-power battery systems but widely supported in legacy designs. | Select when existing 3.3 V infrastructure exists and deep power-down is not required. |
| Micron MT25QL128ABA8ESF-0SIT | 1.8 V nominal supply (compatible range 1.7–2.0 V); identical QPI/Dual/Quad I/O, SFDP, and 21-ball USON package; 10 µA deep power-down (vs. 2 µA). | Same voltage compatibility and feature set; higher deep power-down current reduces battery lifetime advantage. | Select when Micron's qualification ecosystem or specific AEC-Q100 automotive grade is mandated. |
Compared with W25Q128JVSIM and MT25QL128ABA8ESF-0SIT, the AT25SL128A-UIUE-T delivers the lowest deep power-down current (2 µA) and native 1.7–2.0 V operation-critical for energy-constrained edge nodes-while maintaining full QPI/XiP performance parity.
Availability
AT25SL128A-UIUE-T is available at Aetrix Electronics and suitable for industrial PLCs, automotive ADAS modules, IoT edge nodes, medical wearables, and consumer electronics requiring stable component supply with guaranteed long-term manufacturability.
Supply support for AT25SL128A-UIUE-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and memory solutions for industrial, automotive, and IoT markets.
The AT25SL128A product line delivers high-performance, low-voltage serial flash memory optimized for Execute-in-Place (XiP) and secure firmware storage in space- and power-constrained embedded systems.
FAQ
What is the operating voltage range of the AT25SL128A-UIUE-T?
The AT25SL128A-UIUE-T operates within a strict 1.7 V to 2.0 V supply range. This narrow window supports integration with modern low-power SoCs and battery management systems. Operation outside this range may cause undefined behavior or data corruption. The AT25SL128A-UIUE-T does not support 3.3 V or dual-voltage operation.
Does the AT25SL128A-UIUE-T support Execute-in-Place (XiP) functionality?
Yes, the AT25SL128A-UIUE-T explicitly supports XiP through high-speed Quad I/O (0-4-4) and QPI (4-4-4) modes, continuous read with wrap, and 133 MHz maximum clock rate. These features reduce instruction fetch latency and eliminate the need to copy code to RAM before execution. The AT25SL128A-UIUE-T datasheet confirms XiP suitability in Section 1 (Introduction).
What package type is used by the AT25SL128A-UIUE-T?
The AT25SL128A-UIUE-T uses a 21-ball low-profile WLCSP (Wafer-Level Chip Scale Package) with "UI" designation per Renesas ordering information. Its dimensions are 3.0 mm × 2.5 mm × 0.5 mm, making it suitable for ultra-dense PCB layouts in wearables and miniaturized IoT devices. The AT25SL128A-UIUE-T is not offered in SOIC or DFN variants.
How does the write protection mechanism work on the AT25SL128A-UIUE-T?
The AT25SL128A-UIUE-T implements dual-layer write protection: hardware-based via the WP pin (active-low lock), and software-configurable via status register bits BP2–BP0, TB, and SEC. Protection can be applied to top/bottom memory blocks with granularity down to 4 kB. The AT25SL128A-UIUE-T allows independent enable/disable of each layer, ensuring robust defense against accidental or malicious writes.
Is the AT25SL128A-UIUE-T compatible with JEDEC-standard Serial Flash Discovery Parameters (SFDP)?
Yes, the AT25SL128A-UIUE-T fully complies with JEDEC JESD216 standards and includes a readable SFDP register (command 5Ah). This enables automatic host controller detection of timing parameters, erase block sizes, and feature support-eliminating hardcoded configuration tables. The AT25SL128A-UIUE-T SFDP table is documented in Section 8.36 of its datasheet.
AT25SL128A-UIUE-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 21-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 150µs, 5ms
- Access Time:
- 6 ns
- Voltage - Supply:
- 1.7V ~ 2V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 21-WLCSP (3.02x3.29)
AT25SL128A-UIUE-T FAQ
1.How can I place an order for AT25SL128A-UIUE-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SL128A-UIUE-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SL128A-UIUE-T reliable?
The price and inventory of AT25SL128A-UIUE-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SL128A-UIUE-T is usually 5 days.
3.What payment methods are accepted for AT25SL128A-UIUE-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SL128A-UIUE-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SL128A-UIUE-T?
AT25SL128A-UIUE-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SL128A-UIUE-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SL128A-UIUE-T?
For technical support, including AT25SL128A-UIUE-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SL128A-UIUE-T requirements.
6.How does Aetrix verify that AT25SL128A-UIUE-T is sourced from the original manufacturer or authorized distributors?
All AT25SL128A-UIUE-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SL128A-UIUE-T meets industry standards.
7.What is the process for return or replacement of AT25SL128A-UIUE-T?
All AT25SL128A-UIUE-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SL128A-UIUE-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SL128A-UIUE-T part is unused and in its original packaging.
Return procedure for AT25SL128A-UIUE-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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