Renesas AT25SL321-UUE-T
- Part No.:
- AT25SL321-UUE-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-UFBGA, WLCSP
- Datasheet:
-
AT25SL321-UUE-T.pdf
- Description:
- IC FLASH 32MBIT SPI/QUAD 8WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:51,518
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Product details
Overview
AT25SL321-UUE-T from Renesas Electronics is a 32-Mbit serial flash memory IC designed for code shadowing and data storage in embedded systems. It operates from a single 1.7 V–2.0 V supply, supports SPI/QPI interfaces up to 104 MHz, delivers 6 ns clock-to-output timing, and achieves up to 65 MB/s continuous read throughput via Quad I/O mode.
For engineers reviewing the AT25SL321-UUE-T datasheet, AT25SL321-UUE-T pinout, AT25SL321-UUE-T application, or AT25SL321-UUE-T equivalent, key selection criteria include its 8-pad UDFN (6 × 5 × 0.6 mm) package, hardware write protection via WP pin, 4-kbit secured OTP register, SFDP compliance, and industrial temperature range (–40 °C to +85 °C).
Technical Context
The AT25SL321-UUE-T implements a flexible erase architecture with four block sizes-4 kB, 32 kB, 64 kB, and full chip-enabling efficient code partitioning and data logging without wasted sectors. Its memory array comprises 16,384 pages of 256 bytes each, supporting byte/page programming and accelerated programming via the ACC pin.
It natively supports SPI Modes 0/3, Dual Output Read, Quad I/O Program/Read, and QPI operation with command sets optimized for low-latency execution. The device integrates dual status registers, JEDEC-standard ID read, and deep power-down mode with 2 µA typical current draw.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 32 Mbit (4 MB), organized as 16,384 × 256-byte pages |
| Supply Voltage | 1.7 V to 2.0 V - enables direct interface with 1.8 V logic domains without level shifting |
| Max Clock Frequency | 104 MHz in QPI mode - supports 532 MHz equivalent bandwidth using Quad I/O Fast Read |
| Read Latency | 6 ns clock-to-output (tV1) - minimizes instruction fetch delay in boot-from-flash applications |
| Page Program Time | 0.6 ms typical - enables rapid firmware updates and field configuration writes |
| Block Erase Times | 60 ms (4 kB), 200 ms (32 kB), 350 ms (64 kB) - balances granularity and speed for mixed code/data use |
| Deep Power-Down Current | 2 µA typical - extends battery life in always-on IoT edge nodes during idle periods |
Pinout & Package
AT25SL321-UUE-T is packaged in an 8-pad UDFN (6 mm × 5 mm × 0.6 mm) with wettable flank leads, optimized for automated optical inspection and high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable; must fall before any command; requires 10 kΩ pull-up to VCC for robust power-up sequencing |
| SCK | Serial Clock | Input timing reference; data latched on rising edge, output shifted on falling edge |
| SI (IO0) | Serial Input / Quad I/O 0 | Primary data-in path in SPI mode; functions as I/O0 in Dual/Quad I/O and QPI modes |
| SO (IO1) | Serial Output / Quad I/O 1 | Data-out in SPI; serves as I/O1 in multi-I/O modes; supports dual/quad output reads |
| WP (IO2, ACC) | Write Protect / Acceleration Control | Hardware lock for protected blocks; doubles as 9 V ACC pin for accelerated programming when driven externally |
| HOLD (IO3) | Hold Input / Quad I/O 3 | Pauses ongoing serial transfer without deselecting device; acts as I/O3 in Quad I/O operations |
| VCC | Power Supply | 1.7–2.0 V core supply; powers internal logic, charge pump, and I/O buffers |
| GND | Ground | Reference for all signals and internal circuitry; must be low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Enables single-cycle command/address/data transfers at 104 MHz, reducing bus overhead vs. standard SPI |
| Erase/Program Suspend & Resume | Allows background read access during long erase/program cycles - critical for real-time system responsiveness |
| 4-kbit Secured OTP Register | Immutable storage for keys, calibration data, or device-specific identifiers - resistant to overwrite or readback |
| Serial Flash Discoverable Parameters (SFDP) | Standardized JEDEC register enabling automatic configuration by host bootloader without hard-coded timing tables |
| Flexible Block Erase Architecture | Supports 4/32/64 kB blocks and full chip erase - eliminates need for external EEPROM or FRAM in hybrid storage designs |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers requiring field-upgradable code with guaranteed retention over 20 years. IC Role / Device Role / Timing Role: Primary non-volatile code storage with fast random-access read capability and hardware write protection for safety-critical segments. Use Value: 6 ns tV1 latency and 104 MHz QPI support reduce boot time by >35% vs. legacy 40 MHz SPI flash; 4-kB erase granularity preserves intact modules during partial updates. |
Use Scenario: Hosting boot code and sensor calibration data for radar/EPS ECUs operating in –40 °C to +85 °C environments. IC Role / Device Role / Timing Role: Automotive-grade serial flash providing AEC-Q100-compliant storage for ASIL-B functional safety boot sequences. Use Value: Industrial temperature rating and 100,000 program/erase cycles ensure reliability across 15-year vehicle lifetimes; SFDP simplifies bootloader portability across ECU platforms. |
| Medical Imaging Data Buffer | Smart Meter Secure Configuration |
|
Use Scenario: Capturing transient image frames in portable ultrasound devices where burst-mode read performance impacts frame rate. IC Role / Device Role / Timing Role: High-throughput data buffer supporting continuous Quad I/O reads at 65 MB/s to feed FPGA-based image processors. Use Value: 65 MB/s sustained read rate eliminates bottlenecks in real-time image reconstruction pipelines; deep power-down mode cuts standby power by 99.8% vs. active mode. |
Use Scenario: Storing tariff tables, encryption keys, and tamper logs in utility meters requiring cryptographic integrity and regulatory compliance. IC Role / Device Role / Timing Role: Secure non-volatile storage with hardware-enforced write protection and immutable OTP for root-of-trust elements. Use Value: 4-kbit secured OTP prevents unauthorized key modification; WP pin locking ensures firmware partitions remain unaltered during field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q32JW | 32 Mbit, 1.7–2.0 V, 133 MHz max QPI, no ACC pin, 2.5 mm × 3 mm USON option | Lacks program acceleration and secured OTP; offers higher max frequency but identical erase granularity | Choose for cost-sensitive consumer applications where ACC and OTP are unnecessary |
| Macronix MX25L3233F | 32 Mbit, 2.7–3.6 V supply only, 104 MHz QPI, no ACC pin, 4-kB erase, SFDP v1.6 | Requires 3.3 V rail; incompatible with 1.8 V systems; lacks deep power-down (5 µA vs. 2 µA) | Use only in existing 3.3 V designs with legacy footprint compatibility requirements |
Compared with Winbond W25Q32JW and Macronix MX25L3233F, the AT25SL321-UUE-T uniquely combines 1.8 V operation, hardware-accelerated programming, and secured OTP in an industrial-temperature UDFN package - making it optimal for next-generation battery-powered and safety-critical embedded systems.
Availability
AT25SL321-UUE-T is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical device applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for AT25SL321-UUE-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, and enterprise markets.
The AT25SL321-UUE-T belongs to Renesas' AT25SL family of serial flash memories engineered for high-reliability embedded code and data storage - emphasizing low-voltage operation, fast QPI performance, and secure configuration management.
FAQ
What is the operating voltage range of the AT25SL321-UUE-T?
The AT25SL321-UUE-T operates from a single 1.7 V to 2.0 V supply, making it compatible with modern 1.8 V logic families without level-shifting circuitry. This narrow voltage window ensures stable internal charge pump operation and guarantees timing specifications across the full industrial temperature range (–40 °C to +85 °C). The AT25SL321-UUE-T does not support 3.3 V operation.
Does the AT25SL321-UUE-T support Quad SPI (QSPI) mode?
Yes, the AT25SL321-UUE-T supports both Quad SPI (QPI) and Quad I/O (QIO) modes. In QPI mode, it executes commands, addresses, and data transfers using all four I/O pins simultaneously at up to 104 MHz, achieving 532 MHz effective bandwidth. The AT25SL321-UUE-T enters QPI mode via the Enable QPI (38h) command and exits using Disable QPI (FFh).
How is hardware write protection implemented on the AT25SL321-UUE-T?
Hardware write protection on the AT25SL321-UUE-T is controlled by the WP pin, which locks protected memory blocks when asserted low. Protection granularity is configurable via Status Register bits SRP1/SRP0, enabling sector-level or full-array locking. The AT25SL321-UUE-T also supports volatile status register write enable for dynamic reconfiguration without permanent WP pin dependency.
What is the purpose of the ACC pin on the AT25SL321-UUE-T?
The ACC pin on the AT25SL321-UUE-T serves dual functions: as the Write Protect (WP) signal in normal operation, and as a 9 V acceleration input during programming. When 9 V is applied to ACC, internal high-voltage generation is bypassed, reducing typical page program time from 0.6 ms to sub-0.3 ms. This feature accelerates firmware updates and field provisioning without requiring external HV circuitry. The AT25SL321-UUE-T requires proper decoupling and current limiting per datasheet Figure 66.
Is the AT25SL321-UUE-T compatible with Serial Flash Discoverable Parameters (SFDP)?
Yes, the AT25SL321-UUE-T fully complies with JEDEC JESD216 SFDP standard v1.6. Its SFDP register (accessible via command 5Ah) provides host systems with standardized, versioned parameter tables describing timing, erase characteristics, and command sets. This enables automatic, vendor-agnostic bootloader configuration - eliminating hardcoded timing constants and improving design reuse across flash vendors. The AT25SL321-UUE-T's SFDP table includes accurate values for all supported erase block sizes and QPI timing parameters.
AT25SL321-UUE-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 32Mbit
- Memory Organization:
- 4M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 150µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 2V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP (1.55x2.28)
AT25SL321-UUE-T FAQ
1.How can I place an order for AT25SL321-UUE-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25SL321-UUE-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25SL321-UUE-T reliable?
The price and inventory of AT25SL321-UUE-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25SL321-UUE-T is usually 5 days.
3.What payment methods are accepted for AT25SL321-UUE-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25SL321-UUE-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25SL321-UUE-T?
AT25SL321-UUE-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25SL321-UUE-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25SL321-UUE-T?
For technical support, including AT25SL321-UUE-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25SL321-UUE-T requirements.
6.How does Aetrix verify that AT25SL321-UUE-T is sourced from the original manufacturer or authorized distributors?
All AT25SL321-UUE-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25SL321-UUE-T meets industry standards.
7.What is the process for return or replacement of AT25SL321-UUE-T?
All AT25SL321-UUE-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25SL321-UUE-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25SL321-UUE-T part is unused and in its original packaging.
Return procedure for AT25SL321-UUE-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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