Renesas AT25XE011-XMHN-B
- Part No.:
- AT25XE011-XMHN-B
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
AT25XE011-XMHN-B.pdf
- Description:
- IC FLASH 1MBIT SPI 104MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,398
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25XE011-XMHN-B from Renesas Electronics is a 1-Mbit SPI serial flash memory IC optimized for ultra-low-energy IoT and embedded systems, operating from 1.65 V to 3.6 V, supporting SPI Modes 0/3 and Dual-Output Read at up to 104 MHz, with 6 ns clock-to-output delay and hardware write protection via WP pin - deployed in firmware storage, OTA update buffers, and secure boot code retention.
For engineers reviewing the AT25XE011-XMHN-B datasheet, AT25XE011-XMHN-B pinout, AT25XE011-XMHN-B application, or AT25XE011-XMHN-B equivalent, key selection criteria include dual-read throughput, 256-byte page erase granularity, OTP security register usage, ultra-deep power-down current (200 nA), and compatibility with 1.65 V minimum supply rails in space-constrained industrial sensors and battery-powered edge nodes.
Technical Context
The AT25XE011-XMHN-B implements a flexible erase architecture with three granular levels: 256-byte page, 4-kByte block, and 32-kByte block - enabling efficient code/data co-location without over-erasure. Its Dual-Output Read mode uses both SI and SO pins as data outputs, doubling read bandwidth versus standard SPI read.
It integrates a 128-byte OTP security register (64 bytes factory-programmed unique ID + 64 bytes user-programmable) and supports hardware locking via active-low WP pin, while maintaining JEDEC-standard Manufacturer/Device ID read capability and software-controlled reset - all within a single 1.65–3.6 V supply domain.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Mbit (128 KBytes) - sufficient for bootloader, firmware partitions, and configuration data in compact MCU-based designs. |
| Supply Voltage | 1.65 V to 3.6 V - enables direct interface with low-voltage MCUs (e.g., ARM Cortex-M0+, RISC-V) without level-shifting. |
| Max Clock Frequency | 104 MHz - delivers high-speed read access for real-time firmware execution and rapid OTA patch loading. |
| Read Latency | 6 ns clock-to-output (tV) - minimizes instruction fetch stalls in XIP (execute-in-place) configurations. |
| Erase Granularity | 256-byte page / 4-kByte block / 32-kByte block - allows precise firmware delta updates and avoids full-chip erases during field upgrades. |
| Power-Down Current | 200 nA ultra-deep power-down (typical) - extends battery life in always-on sensor nodes and wearable devices. |
| Endurance & Retention | 100,000 program/erase cycles / 20-year data retention - meets long-lifecycle requirements for industrial gateways and medical telemetry. |
Pinout & Package
AT25XE011-XMHN-B is packaged in an 8-lead SOIC (150-mil) - industry-standard surface-mount footprint compatible with automated assembly and reflow processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable signal; must transition high-to-low to initiate commands and low-to-high to terminate - controls device selection and SO high-impedance state. |
| SCK | Serial Clock | Master-generated clock; rising edge latches SI input, falling edge clocks SO output - supports SPI Modes 0 and 3 only. |
| SI (I/O0) | Serial Input / Dual-Read Output | Input for commands/addresses/data; becomes output (I/O0) during Dual-Output Read to deliver LSB of each byte alongside SO (I/O1). |
| SO (I/O1) | Serial Output / Dual-Read Output | Primary output for standard reads; remains I/O1 during Dual-Output Read to deliver MSB of each byte in parallel with SI. |
| WP | Write Protect | Active-low hardware lock; when asserted, prevents status register writes and sector protection changes - ensures firmware integrity against accidental overwrite. |
| HOLD | Communication Hold | Active-low pause signal; suspends ongoing SPI transfers without deselecting device or resetting internal state - useful for interrupt handling in time-critical systems. |
| VCC | Power Supply | Single 1.65–3.6 V supply; powers all logic and memory array - eliminates need for charge pumps or auxiliary voltage rails. |
| GND | Ground Reference | System ground return path; must be low-impedance connection to minimize noise coupling into sensitive SPI timing paths. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Output Read Mode | Enables 2-bit-per-clock read throughput using SI and SO simultaneously - cuts read time by ~50% vs. standard SPI, accelerating firmware validation and OTA verification. |
| 256-Byte Page Erase | Allows minimal-impact updates to individual configuration parameters or calibration tables without disturbing adjacent code or data sectors. |
| 128-Byte OTP Security Register | Provides tamper-resistant storage for unique device identifiers, cryptographic keys, or secure boot hashes - 64 bytes factory-programmed, 64 bytes user-writable once. |
| Ultra-Deep Power-Down | Reduces current draw to 200 nA (typical), enabling multi-year operation on coin-cell batteries in wireless sensor networks and asset trackers. |
| Hardware Write Protection | WP pin assertion locks protected memory sectors at hardware level - immune to software crashes or malware-induced writes during field deployment. |
Applications
| Smart Meter Firmware Storage | Industrial Sensor Node Data Logging |
|---|---|
Use Scenario: Storing metrology firmware, calibration coefficients, and regulatory compliance data in ANSI C12.19-compliant smart electricity meters. IC Role / Device Role / Timing Role: Non-volatile code and parameter storage with guaranteed 20-year retention and 100K-cycle endurance under temperature cycling. Use Value: Enables field-upgradable firmware without meter replacement, leveraging 256-byte page erase to minimize downtime during utility-side OTA deployments. | Use Scenario: Capturing timestamped sensor readings (temperature, humidity, vibration) in IIoT edge nodes powered by primary lithium batteries. IC Role / Device Role / Timing Role: Low-power data buffer with ultra-deep power-down (200 nA) between sampling intervals and fast wake/read capability (6 ns tV). Use Value: Extends battery life beyond 10 years by minimizing active current (3.5 mA typical read) and eliminating standby leakage above 25 µA. |
| Secure Bootloader Storage | Wireless Module Configuration Storage |
Use Scenario: Holding immutable root-of-trust code and public key certificates for secure boot in cellular (LTE-M/NB-IoT) and LoRaWAN modules. IC Role / Device Role / Timing Role: Trusted firmware vault with hardware write protection (WP pin) and OTP-secured key storage preventing runtime corruption. Use Value: Prevents unauthorized firmware injection by enforcing hardware-level lock on boot partition - validated via factory-programmed 64-byte unique ID. | Use Scenario: Storing RF calibration data, MAC addresses, and network credentials in compact Wi-Fi/BLE modules used in consumer appliances. IC Role / Device Role / Timing Role: Compact, low-voltage (1.65 V min) configuration store interfaced directly to 1.8 V host SoCs without level shifters. Use Value: Reduces BOM count and PCB area by eliminating external voltage translators while maintaining reliable SPI communication at 104 MHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q01JV-IQ | 1 Mbit, 1.7–3.6 V supply, 133 MHz max clock, no Dual-Output Read, 1.5 ms page program (vs. 2 ms), 100K endurance. | Lacks Dual-Output Read and ultra-deep power-down (1 µA deep PD vs. 200 nA); higher voltage floor limits use with sub-1.7 V MCUs. | Select when maximum read speed is critical and ultra-low-power sleep is secondary; verify host SPI driver supports standard Quad I/O if migrating from Dual-Output. |
| Micron MT25QL01GBBB8E12-0SIT | 1 Gbit (not 1 Mbit), 1.7–2.0 V or 2.7–3.6 V dual supply, 133 MHz, Quad SPI, 100K endurance, 20-year retention. | 1000× larger capacity, incompatible voltage range (no 1.65 V support), requires Quad SPI controller - not drop-in replaceable. | Choose only for capacity-scaling scenarios where board redesign accommodates different pinout, voltage rails, and driver stack; not suitable for footprint- or voltage-constrained AT25XE011-XMHN-B replacements. |
Compared with W25Q01JV-IQ and MT25QL01GBBB8E12-0SIT, the AT25XE011-XMHN-B uniquely balances ultra-low-voltage operation (1.65 V), dual-read bandwidth, and nanoamp-level power-down - making it optimal for energy-harvesting and coin-cell-powered edge devices where voltage headroom and quiescent current are design-limiting factors.
Availability
AT25XE011-XMHN-B is available at Aetrix Electronics and suitable for smart meter firmware storage, industrial sensor node data logging, secure bootloader storage, and wireless module configuration storage requiring stable component supply across multi-year production cycles.
Supply support for AT25XE011-XMHN-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering trusted microcontrollers, analog, power, and memory solutions for automotive, industrial, infrastructure, and IoT applications.
The AT25XE011-XMHN-B belongs to Renesas' ultra-low-energy serial flash product line, engineered specifically for battery-constrained and energy-harvesting IoT endpoints requiring robust non-volatile storage with minimal voltage and power overhead.
FAQ
What is the minimum operating voltage for the AT25XE011-XMHN-B?
The AT25XE011-XMHN-B operates down to 1.65 V - verified across the full commercial temperature range (-10 °C to +85 °C). This enables direct integration with 1.8 V and lower-voltage MCUs without level-shifting circuitry, unlike alternatives requiring ≥1.7 V. The AT25XE011-XMHN-B maintains full functionality including Dual-Output Read and 104 MHz operation at this minimum rail.
Does the AT25XE011-XMHN-B support Quad SPI mode?
No, the AT25XE011-XMHN-B does not support Quad SPI. It supports standard SPI (single I/O) and Dual-Output Read mode only - where SI and SO function as complementary data outputs during read operations. Quad SPI requires four I/O lines (IO0–IO3), which the AT25XE011-XMHN-B pinout and command set do not implement. The AT25XE011-XMHN-B achieves enhanced throughput solely through its Dual-Output Read capability.
How is the OTP security register structured in the AT25XE011-XMHN-B?
The AT25XE011-XMHN-B contains a 128-byte OTP (One-Time Programmable) Security Register: the first 64 bytes are factory-programmed with a unique device identifier (ESN), and the remaining 64 bytes are user-programmable once. Programming is irreversible and requires specific command sequences (02h for write, 04h for read). This register supports secure boot key storage, device serialization, and anti-counterfeiting - and is protected independently from main array writes.
What erase options are available on the AT25XE011-XMHN-B?
The AT25XE011-XMHN-B offers four erase modes: Byte/Page Erase (1–256 bytes, 2 ms typical), 4-kByte Block Erase (50 ms typical), 32-kByte Block Erase (400 ms typical), and Full Chip Erase. This granular architecture allows targeted updates - for example, modifying a single configuration parameter without erasing adjacent firmware - reducing wear and improving system responsiveness during field updates.
Can the AT25XE011-XMHN-B be used in -40 °C environments?
Yes, the AT25XE011-XMHN-B is rated for operation from -40 °C to +85 °C - but only when supplied with 1.7 V to 3.6 V. At the absolute minimum 1.65 V supply, the specified temperature range is -10 °C to +85 °C. For full industrial temperature compliance, ensure VCC ≥1.7 V in sub-zero applications. All timing, endurance, and retention specifications remain valid across the extended range under these conditions.
AT25XE011-XMHN-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 12µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
AT25XE011-XMHN-B FAQ
1.How can I place an order for AT25XE011-XMHN-B through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25XE011-XMHN-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25XE011-XMHN-B reliable?
The price and inventory of AT25XE011-XMHN-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25XE011-XMHN-B is usually 5 days.
3.What payment methods are accepted for AT25XE011-XMHN-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25XE011-XMHN-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25XE011-XMHN-B?
AT25XE011-XMHN-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25XE011-XMHN-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25XE011-XMHN-B?
For technical support, including AT25XE011-XMHN-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25XE011-XMHN-B requirements.
6.How does Aetrix verify that AT25XE011-XMHN-B is sourced from the original manufacturer or authorized distributors?
All AT25XE011-XMHN-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25XE011-XMHN-B meets industry standards.
7.What is the process for return or replacement of AT25XE011-XMHN-B?
All AT25XE011-XMHN-B units undergo pre-shipment inspection (PSI). If there is an issue with AT25XE011-XMHN-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25XE011-XMHN-B part is unused and in its original packaging.
Return procedure for AT25XE011-XMHN-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25XE011-XMHN-B Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
