Renesas AT25XE161D-MAHN-T
- Part No.:
- AT25XE161D-MAHN-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT25XE161D-MAHN-T.pdf
- Description:
- IC FLASH 16MBIT SPI/QUAD 8USON
- Quantity:
- Payment:

- Shipping:

Inventory:9,454
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT25XE161D from Renesas Electronics is a 16-Mbit SPI serial flash memory IC supporting 1.65 V–3.6 V operation, quad I/O (1-4-4/XiP), 133 MHz max clock, and flexible erase (256-byte page to full chip). It serves as non-volatile program/data storage in boot code loading, execute-in-place (XiP) execution, and embedded data logging.
For engineers reviewing the AT25XE161D datasheet, AT25XE161D pinout, AT25XE161D application, or AT25XE161D equivalent, key selection considerations include XiP support with continuous read mode (0-4-4), ultra-low-power deep power-down (7 nA), 100,000 program/erase cycles, and JEDEC-standard SFDP compliance for automatic configuration.
Technical Context
The AT25XE161D implements a multi-mode SPI interface supporting standard (1-1-1), dual-output (1-1-2), quad-output (1-1-4), quad-I/O (1-4-4), and XiP (0-4-4) protocols - all configurable via command sequences without hardware reconfiguration. Its internal architecture integrates a 256-byte SRAM buffer, status register bank (SR1–SR6), and OTP security registers.
Memory management includes nested erase/program suspend-resume capability, individual block lock/unlock commands (36h/39h), global protection (7Eh/98h), and Read-Modify-Write (0Ah) for EEPROM-emulation behavior. Power control features include Deep Power-Down (B9h) and Ultra-Deep Power-Down (79h) with device-ID-resume (ABh).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 16 Mbit (2 MB) organized as 2,097,152 bytes; enables compact firmware storage for resource-constrained MCUs. |
| Supply Voltage Range | 1.65 V to 3.6 V - supports direct interfacing with 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max Clock Frequency | 133 MHz - delivers up to 532 MB/s effective throughput in quad-I/O (1-4-4) mode for fast XiP performance. |
| Erase Granularity | 256-byte page erase - minimizes write latency and wear for small-data updates like sensor logs or configuration parameters. |
| Endurance & Retention | 100,000 program/erase cycles and 20-year data retention - validated for industrial lifecycle requirements. |
| Ultra-Low Power Modes | 7 nA Ultra Deep Power-Down current - extends battery life in always-on IoT edge nodes during extended sleep intervals. |
| Security Features | 3 × 128-byte One-Time Programmable (OTP) registers + factory-unique 128-byte ID - enables secure key binding and device authentication. |
Pinout & Package
AT25XE161D-MAHN-T uses an 8-pad Ultra-thin DFN package (2 mm × 3 mm × 0.6 mm), RoHS-compliant and halogen-free, optimized for space-constrained PCB layouts in portable and wearable electronics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-low enable for SPI command decoding; must be held low during entire transaction (command + address + data). |
| SCK | Serial Clock | Input clock synchronized to host MCU; supports modes 0 and 3 (CPOL=0/1, CPHA=0/1); max 133 MHz. |
| SI (I/O0) | Serial Input / Quad I/O Lane 0 | Primary data input in standard/dual/quad modes; functions as bidirectional I/O0 in 1-4-4 and 0-4-4 XiP. |
| SO (I/O1) | Serial Output / Quad I/O Lane 1 | Primary data output in standard mode; bidirectional I/O1 in quad-I/O; supports continuous read in XiP. |
| WP (I/O2) | Write Protect / Quad I/O Lane 2 | Hardware write protection when asserted low; also serves as I/O2 in quad-I/O modes for expanded bandwidth. |
| HOLD/RESET (I/O3) | Hold Input or Hardware Reset | Pauses ongoing SPI transfer when held low; alternatively triggers JEDEC-standard hardware reset (active-low pulse ≥ 20 ns). |
| VCC | Power Supply | 1.65 V–3.6 V supply; decoupling capacitor required per datasheet layout guidelines (Section 9.3). |
| GND | Ground | Reference for all I/O and internal circuitry; requires low-impedance connection to minimize noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Execute-in-Place (XiP) Support | Enables direct CPU instruction fetch from flash via 0-4-4 command format - eliminates RAM copy overhead and reduces boot time. |
| Read-Modify-Write (RMW) Command | Single 0Ah command emulates byte-level SRAM writes in flash - simplifies firmware updates without external buffering logic. |
| Active Status Interrupt | Automatically asserts interrupt to host when RDY/BSY bit clears - replaces polling and improves system-level power efficiency. |
| Flexible Memory Protection | Configurable block locking (individual/global), start/end protected area definition, and volatile/non-volatile status register lock - prevents accidental firmware corruption. |
| Serial Flash Discoverable Parameters (SFDP) | JEDEC-standard SFDP table (5Ah command) provides runtime-configurable timing, voltage, and feature parameters - enables plug-and-play driver compatibility. |
Applications
| Industrial PLC Firmware Storage | IoT Edge Sensor Node Logging |
|---|---|
Use Scenario: Storing and updating ladder logic firmware in programmable logic controllers with field-upgrade capability. IC Role / Device Role / Timing Role: Non-volatile program memory with XiP execution and 256-byte page erase for incremental firmware patches. Use Value: Enables zero-downtime firmware updates via partial reprogramming while maintaining real-time control loop integrity. | Use Scenario: Capturing temperature, humidity, and motion events in battery-powered environmental monitors. IC Role / Device Role / Timing Role: Local data logger with ultra-low-power Deep Power-Down (7 nA) between sampling intervals. Use Value: Extends 10-year battery life by minimizing active current (8.3 mA read @104 MHz) and enabling sub-microamp sleep states. |
| Medical Wearable Boot Code | Smart Home Hub Configuration |
Use Scenario: Secure boot image storage in FDA-cleared wearable ECG devices requiring tamper-resistant firmware. IC Role / Device Role / Timing Role: Trusted boot source using factory-programmed unique ID and OTP registers for cryptographic key binding. Use Value: Meets IEC 62304 security requirements through hardware-enforced write protection and immutable device identity. | Use Scenario: Storing Wi-Fi credentials, OTA update metadata, and user preferences in voice-controlled smart home hubs. IC Role / Device Role / Timing Role: Parameter/configuration store with RMW (0Ah) command for atomic settings updates without full-page erases. Use Value: Prevents configuration corruption during power loss by completing byte-level writes in a single atomic operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q16JW | 16 Mbit, 1.7–2.0 V supply only; no Ultra-Deep Power-Down (7 nA); supports 133 MHz quad-I/O but lacks XiP continuous read (0-4-4). | Best suited for 1.8 V systems where ultra-low-power sleep is not required; no native XiP acceleration path. | Select when board already uses 1.8 V rail and XiP performance is secondary to cost. |
| Macronix MX25L1633F | 16 Mbit, 2.7–3.6 V supply; includes 1.8 V I/O support but no 1.65 V min; offers 100 µA standby (vs. 30 µA) and no OTP security registers. | Targeted at 3.3 V industrial designs needing high-temp reliability; lacks factory-unique ID and OTP for secure boot. | Choose for legacy 3.3 V platforms where security features are handled externally. |
Compared with W25Q16JW and MX25L1633F, the AT25XE161D uniquely combines 1.65 V operation, 7 nA UDPD, factory-unique ID, and true 0-4-4 XiP - making it optimal for next-gen ultra-low-power, secure, and boot-critical embedded systems.
Availability
AT25XE161D-MAHN-T is available at Aetrix Electronics and suitable for industrial PLC firmware storage, IoT edge sensor node logging, medical wearable boot code, and smart home hub configuration requiring stable component supply across long-lifecycle deployments.
Supply support for AT25XE161D-MAHN-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, and IoT markets.
The AT25XE161D belongs to Renesas' AT25XE family of high-reliability serial flash memories engineered for ultra-low-power, secure, and XiP-capable embedded applications demanding extended battery life and firmware integrity.
FAQ
What is the minimum operating voltage for the AT25XE161D-MAHN-T?
The AT25XE161D-MAHN-T operates down to 1.65 V, enabling direct integration into 1.8 V and even some 1.2 V–1.8 V hybrid power domains with appropriate regulation. This low-voltage capability supports energy harvesting and coin-cell-powered devices where supply headroom is constrained, and is verified across the full -40°C to +85°C temperature range per datasheet Section 7.2.
Does the AT25XE161D-MAHN-T support execute-in-place (XiP) operation?
Yes, the AT25XE161D-MAHN-T fully supports XiP via its 0-4-4 command mode, which eliminates opcode transmission after initial setup and enables continuous burst reads directly into the host processor's instruction pipeline. This feature is implemented in hardware and documented in Sections 4.6 and 6.34 of the datasheet, with timing validated up to 133 MHz.
How does the Read-Modify-Write (RMW) command work on the AT25XE161D-MAHN-T?
The AT25XE161D-MAHN-T implements RMW using the dedicated 0Ah command, which internally performs a read-erase-modify-program sequence in a single atomic operation. It targets one byte or word, avoids external SRAM buffering, and ensures data consistency during power loss - critical for configuration storage in safety-critical systems.
What security features are built into the AT25XE161D-MAHN-T?
The AT25XE161D-MAHN-T includes three 128-byte One-Time Programmable (OTP) security registers, a factory-programmed 128-byte unique identifier, individual and global block lock commands (36h/7Eh), and status register lock (6Fh). These features collectively enable secure key injection, device authentication, and firmware write protection - all defined in Sections 4.11 and 4.8 of the official datasheet.
What package type is used by the AT25XE161D-MAHN-T?
The AT25XE161D-MAHN-T uses an 8-pad Ultra-thin DFN package measuring 2 mm × 3 mm × 0.6 mm (body), with exposed pad thermal enhancement and RoHS-compliant, halogen-free construction. Pinout matches standard SOIC-8 but in a 60% smaller footprint, as specified in Section 9.3 of the datasheet and ordering code "MAHN".
AT25XE161D-MAHN-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 16Mbit
- Memory Organization:
- 2M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 20µs, 12ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT25XE161D-MAHN-T FAQ
1.How can I place an order for AT25XE161D-MAHN-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT25XE161D-MAHN-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT25XE161D-MAHN-T reliable?
The price and inventory of AT25XE161D-MAHN-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT25XE161D-MAHN-T is usually 5 days.
3.What payment methods are accepted for AT25XE161D-MAHN-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT25XE161D-MAHN-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT25XE161D-MAHN-T?
AT25XE161D-MAHN-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT25XE161D-MAHN-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT25XE161D-MAHN-T?
For technical support, including AT25XE161D-MAHN-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT25XE161D-MAHN-T requirements.
6.How does Aetrix verify that AT25XE161D-MAHN-T is sourced from the original manufacturer or authorized distributors?
All AT25XE161D-MAHN-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT25XE161D-MAHN-T meets industry standards.
7.What is the process for return or replacement of AT25XE161D-MAHN-T?
All AT25XE161D-MAHN-T units undergo pre-shipment inspection (PSI). If there is an issue with AT25XE161D-MAHN-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT25XE161D-MAHN-T part is unused and in its original packaging.
Return procedure for AT25XE161D-MAHN-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT25XE161D-MAHN-T Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

