Microchip Technology AT27C010-90JC
- Part No.:
- AT27C010-90JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT27C010-90JC.pdf
- Description:
- IC EPROM 1MBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT27C010-90JC from Atmel is a 1-Mbit (128K × 8) one-time programmable EPROM designed for firmware storage in microprocessor systems. It features 45 ns read access time, 5V ±10% supply operation, and JEDEC-standard 32-lead PLCC packaging. Its dual-line control (CE/OE), rapid 100 µs/byte programming, and integrated product identification code support reliable boot code retention in industrial controllers and legacy embedded systems.
For engineers reviewing the AT27C010-90JC datasheet, AT27C010-90JC pinout, AT27C010-90JC application, or AT27C010-90JC equivalent, key selection criteria include verified 90 ns AC timing compliance, VPP = 12.0 V programming voltage, CMOS/TTL I/O compatibility, standby current ≤100 µA, and PLCC package thermal performance across 0°C to 70°C commercial operation.
Technical Context
The AT27C010-90JC implements a standard OTP EPROM architecture with address decoding for A0–A16, eight bidirectional data outputs (O0–O7), and dedicated PGM strobe for high-voltage programming. Its two-line enable scheme (CE and OE) enables precise bus contention control during read cycles.
It supports Rapid™ programming using 100 µs pulses at VPP = 12.0 V ±0.5 V and VCC = 6.5 V ±0.25 V, with built-in verification loops per byte. Product identification is accessed via A9 = 12.0 V and A0 toggling, returning manufacturer (0x1E) and device (0x05) codes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1,048,576-bit (128K × 8) OTP EPROM - fixed firmware storage without reprogrammability. |
| Read Access Time | 90 ns max - ensures no WAIT states required on 11 MHz Z80 or 8 MHz 8086 systems. |
| VCC Supply | 5 V ±10% - compatible with standard TTL/CMOS logic rails; no auxiliary voltage needed for read mode. |
| Standby Current | 100 µA max - enables low-power hold state in battery-backed or energy-constrained systems. |
| Active Current | 35 mA max at 5 MHz - defines power budget for sustained read bursts in real-time firmware fetch. |
| VPP Programming Voltage | 12.0 V ±0.5 V - requires external high-voltage supply; not used during normal read operation. |
| Operating Temperature | 0°C to 70°C - commercial-grade thermal range suitable for office, lab, and non-harsh industrial environments. |
Pinout & Package
AT27C010-90JC is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), JEDEC MS-016 AE compliant, with 1.27 mm pitch and body size 18.5 × 18.5 mm. Pin 1 is marked by index notch; leads are gull-wing shaped for surface-mount soldering.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus interface; selects one of 131,072 bytes; A0 = LSB, A16 = MSB. |
| O0–O7 | Data Outputs | 8-bit bidirectional data bus; outputs valid when CE = OE = low; high-impedance when disabled. |
| CE | Chip Enable | Primary device select; must be low for read or program access; controls VCC current draw. |
| OE | Output Enable | Secondary output gate; allows shared bus operation without disabling chip; float control independent of CE. |
| PGM | Program Strobe | Active-low pulse input; initiates byte programming when VPP = 12 V and CE = low. |
| VCC | Power Supply | +5 V supply for logic and read operations; must be applied before/removed after VPP during programming. |
| VPP | Programming Voltage | +12 V supply input only during programming; disconnected or tied to VCC in read mode. |
| GND | Ground | Reference node for all signals and supplies; requires local 0.1 µF ceramic decoupling. |
| NC | No Connect | Pin 14 (PLCC) is unconnected; must remain floating - no external tie or pull-up/down. |
Key Features
| Feature | Design Value |
|---|---|
| Rapid™ Programming Algorithm | 100 µs/byte typical programming time with automatic verify-reprogram loop - reduces production burn-in time by >70% vs. legacy EPROMs. |
| Integrated Product Identification Code | Manufacturer ID (0x1E) and Device ID (0x05) readable via A9 = 12 V and A0 toggle - enables automated programmer validation and BOM traceability. |
| Two-Line Control (CE/OE) | Independent chip and output enables - eliminates bus contention in multi-device memory maps and supports interleaved read architectures. |
| High-Reliability CMOS Process | 2000 V HBM ESD rating and 200 mA latchup immunity - ensures robustness during handling, PCB assembly, and field operation. |
| JEDEC-Standard Packages | 32-lead PLCC (32J) footprint - supports drop-in replacement in legacy designs using Atmel's AT27C010 family without layout change. |
Applications
| Industrial PLC Firmware Storage | Legacy Microcontroller Boot ROM |
|---|---|
|
Use Scenario: Storing fixed ladder logic and I/O configuration in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile boot memory mapped to CPU address space; provides deterministic 90 ns instruction fetch latency. Use Value: Eliminates reliance on slow serial EEPROM or volatile RAM + battery backup; ensures immediate, repeatable startup after power cycle. |
Use Scenario: Hosting immutable BIOS or monitor firmware for 8-bit/16-bit microcontrollers (e.g., Z80, 8086) in test equipment and medical analyzers. IC Role / Device Role / Timing Role: Primary read-only code store; accessed during reset vector fetch and early initialization phase. Use Value: Guarantees bit-identical firmware execution across units; avoids corruption risks associated with flash wear or write errors. |
| Automated Test Equipment (ATE) Pattern Memory | Avionics Display Controller Firmware |
|
Use Scenario: Holding fixed test pattern sequences in semiconductor ATE handlers where repeatability and timing stability are critical. IC Role / Device Role / Timing Role: Static pattern buffer accessed via DMA controller; timing-critical due to synchronized waveform generation. Use Value: Delivers jitter-free 90 ns access to pattern bytes, enabling sub-microsecond trigger alignment across parallel channels. |
Use Scenario: Storing display initialization routines and font glyphs in cockpit display units certified to DO-254 Level A/B. IC Role / Device Role / Timing Role: Safety-critical firmware image stored in tamper-proof OTP; verified at power-on self-test (POST). Use Value: Meets RTCA DO-254 requirements for immutable, radiation-tolerant code storage without runtime update capability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar OTP EPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT27C020-90JC | 2-Mbit (256K × 8) capacity; identical 90 ns timing, PLCC-32 package, and programming algorithm. | Supports larger firmware images; requires wider address bus (A0–A17) and updated decode logic. | Select when firmware exceeds 128K bytes and board layout accommodates extended addressing. |
| MX27C1000-90PC | Same 1-Mbit density and 90 ns speed, but in PDIP-32; VPP = 12.5 V; no integrated ID code. | Lacks product identification feature; requires manual programmer setup; suited for cost-sensitive through-hole designs. | Choose for legacy through-hole assembly or where PLCC rework capability is unavailable. |
Compared with AT27C010-90JC, AT27C020-90JC doubles storage while maintaining pinout and timing, whereas MX27C1000-90PC trades ID functionality and package type for PDIP compatibility-neither is pin-compatible, but both serve overlapping firmware storage roles with verified 90 ns read performance.
Availability
AT27C010-90JC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy microcontroller boot ROM, automated test equipment pattern memory, and avionics display controller firmware requiring stable component supply and long-term obsolescence management.
Supply support for AT27C010-90JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT27C010(L) product line was engineered for high-reliability, low-power OTP EPROM applications in industrial, automotive, and communications systems where firmware immutability and timing predictability are essential.
FAQ
What is the maximum operating temperature range for the AT27C010-90JC?
The AT27C010-90JC is rated for commercial operation from 0°C to 70°C. This range is explicitly defined in the ordering information table for the "-90JC" suffix, where "C" denotes Commercial grade. It is not qualified for industrial (-40°C to +85°C) or automotive (-40°C to +125°C) temperature ranges - those require suffixes "-90JI" or "-90JA", respectively. The AT27C010-90JC must be used within its specified 0°C–70°C ambient envelope to guarantee 90 ns access time and 100 µA standby current.
Does the AT27C010-90JC require a separate VPP supply during normal read operation?
No, the AT27C010-90JC does not require VPP during normal read operation. VPP is only active during programming and must be set to 12.0 V ±0.5 V. In read mode, VPP may be left unconnected or tied to VCC (5 V), as stated in the DC Operating Conditions. Applying 12 V to VPP during read will exceed absolute maximum ratings and risk permanent damage. The AT27C010-90JC draws power solely from VCC (5 V ±10%) during read, consuming up to 35 mA at 5 MHz.
Can the AT27C010-90JC be programmed in-system, or does it require a dedicated EPROM programmer?
The AT27C010-90JC requires a dedicated EPROM programmer capable of delivering 12.0 V to VPP and generating precise 100 µs PGM pulses under controlled timing (tAS, tCES, tPW). In-system programming is not supported because the device lacks internal charge pumps or ISP circuitry; its Rapid™ algorithm relies on external high-voltage control and verification logic. Standard microcontroller ISP interfaces cannot replicate the required VPP sequencing or byte-level verify-reprogram loops. Programming must occur off-board using certified equipment such as BP Microsystems or Xeltek programmers.
What is the function of the NC pin on the AT27C010-90JC PLCC package?
Pin 14 on the AT27C010-90JC PLCC (32J) package is designated NC (No Connect) and must remain electrically floating - it is not bonded internally and has no circuit function. The datasheet explicitly identifies this pin as NC in the PLCC top view diagram and warns against tying it to VCC, GND, or any signal. Connecting the NC pin may cause unpredictable behavior or violate JEDEC mechanical specifications. All functional signals (A0–A16, O0–O7, CE, OE, PGM, VCC, VPP, GND) are assigned to other pins; NC serves only as a mechanical placeholder.
How is the Integrated Product Identification Code read from the AT27C010-90JC?
The Integrated Product Identification Code of the AT27C010-90JC is read by applying 12.0 V ±0.5 V to A9 (VID pin), holding A1–A16 low, and toggling A0 between low (VIL) and high (VIH) while keeping CE = OE = VIL. When A0 = VIL, the Manufacturer ID (0x1E) appears on O7–O0; when A0 = VIH, the Device ID (0x05) appears. This sequence requires precise voltage control on A9 and is supported only by programmers compliant with Atmel's identification protocol - standard memory readers without VID-capable hardware cannot access this code.
AT27C010-90JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EPROM
- Technology:
- EPROM - OTP
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- -
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT27C010-90JC FAQ
1.How can I place an order for AT27C010-90JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT27C010-90JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT27C010-90JC reliable?
The price and inventory of AT27C010-90JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT27C010-90JC is usually 5 days.
3.What payment methods are accepted for AT27C010-90JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT27C010-90JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT27C010-90JC?
AT27C010-90JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT27C010-90JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT27C010-90JC?
For technical support, including AT27C010-90JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT27C010-90JC requirements.
6.How does Aetrix verify that AT27C010-90JC is sourced from the original manufacturer or authorized distributors?
All AT27C010-90JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT27C010-90JC meets industry standards.
7.What is the process for return or replacement of AT27C010-90JC?
All AT27C010-90JC units undergo pre-shipment inspection (PSI). If there is an issue with AT27C010-90JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT27C010-90JC part is unused and in its original packaging.
Return procedure for AT27C010-90JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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