Microchip Technology AT27C020-55JC
- Part No.:
- AT27C020-55JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT27C020-55JC.pdf
- Description:
- IC EPROM 2MBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT27C020-55JC from Atmel is a 2-Mbit (256K × 8) one-time programmable EPROM with 55 ns read access time, 5V ±10% supply operation, and JEDEC-standard 32-lead PLCC package. It delivers low active current (25 mA max at 5 MHz), ultra-low standby current (100 µA max), and supports commercial temperature range (0°C to 70°C). Used in firmware storage for microprocessor-based embedded systems where non-volatility and fast random-access boot code retrieval are required.
For engineers reviewing the AT27C020-55JC datasheet, AT27C020-55JC pinout, AT27C020-55JC application, or AT27C020-55JC equivalent, key selection considerations include its OTP architecture, dual-line control (CE/OE), Rapid™ programming algorithm (100 µs/byte), integrated product identification code, and compatibility with CMOS/TTL bus interfaces.
Technical Context
The AT27C020-55JC implements a two-line enable architecture (CE and OE) to eliminate bus contention during read operations, enabling direct integration into high-speed microprocessor data buses without WAIT-state insertion. Its address space spans A0–A17 (18-bit), supporting full 256K-byte decoding with byte-wide parallel outputs O0–O7.
Programming requires VPP = 13.0 V ±0.25 V and VCC = 6.5 V ±0.25 V, with a 100 µs PGM pulse width and verification loop per byte. Product identification uses A9 voltage (12.0 V ±0.5 V) and A0 toggling to select manufacturer (0x1E) or device code (0x86) bytes - a feature used by industry-standard programmers for auto-algorithm selection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2,097,152 bits (256K × 8) - provides sufficient space for boot firmware or configuration tables in 8-bit microcontroller systems. |
| Read Access Time | 55 ns - enables zero-WAIT-state operation with 18 MHz+ microprocessors, eliminating timing bottlenecks in critical boot paths. |
| Supply Voltage | 5V ±10% - compatible with legacy 5V logic families and eliminates need for auxiliary voltage regulators. |
| Active Current | 25 mA max at 5 MHz - ensures stable power delivery without excessive thermal load in dense PCB layouts. |
| Standby Current | 100 µA max - supports low-power system sleep modes while retaining firmware integrity. |
| Programming Speed | 100 µs/byte typical - reduces production programming cycle time versus standard EPROMs, improving throughput in firmware loading stations. |
| ESD Protection | 2,000V HBM - enhances handling robustness during manual assembly or field rework without requiring special ESD protocols. |
Pinout & Package
AT27C020-55JC is housed in a 32-lead Plastic J-leaded Chip Carrier (PLCC), JEDEC MS-016 AE compliant, with 1.27 mm pitch and 11.4 mm × 11.4 mm body size. Pin 1 is marked by index notch and corner chamfer.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A17 | Address Inputs | 18-bit address bus interface; fully decodes 256K-byte space - no external address latching required. |
| O0–O7 | Data Outputs | True TTL/CMOS-compatible bidirectional data bus drivers - directly connect to 8-bit microprocessor data lines. |
| CE | Chip Enable | Primary device select; when high, forces outputs to high-impedance regardless of OE state - essential for multi-device memory mapping. |
| OE | Output Enable | Secondary output gate; allows shared bus operation with CE asserted - enables interleaved read timing control. |
| PGM | Program Strobe | Active-low programming trigger; initiates 100 µs internal write pulse when VPP = 13 V - only active during factory or lab programming. |
| VPP | Programming Voltage | 13.0 V ±0.25 V input during programming; must be applied after and removed before VCC - prevents inadvertent writes in system operation. |
| VCC | Power Supply | 5V ±10% main supply; powers logic and outputs during read mode - no separate I/O or core voltage rails needed. |
| GND | Ground Reference | Common return path for VCC and VPP; requires local 0.1 µF ceramic decoupling per device per datasheet layout guidance. |
Key Features
| Feature | Design Value |
|---|---|
| Rapid™ Programming Algorithm | Reduces average programming time to ~100 µs/byte with automatic verify-reprogram loops - cuts firmware update time in manufacturing test by >60% vs. legacy EPROMs. |
| Integrated Product ID Code | Manufacturer (0x1E) and device (0x86) codes readable via A9/VH + A0 toggle - enables automated programmer validation and BOM traceability without external labeling. |
| Two-Line Control (CE/OE) | Independent chip and output enables allow flexible bus arbitration - supports glueless interfacing with Intel- and Motorola-style microprocessor buses. |
| JEDEC-Standard Packages | Available in PLCC (32J), PDIP (32P6), and TSOP (32T) - permits drop-in replacement across board revisions without footprint redesign. |
| High-Reliability Process | 200 mA latch-up immunity and 2,000 V ESD protection - ensures field reliability in industrial environments with noisy power or frequent handling. |
Applications
| Industrial PLC Firmware Storage | Legacy Embedded Boot ROM |
|---|---|
Use Scenario: Storing fixed ladder logic execution firmware in programmable logic controllers operating in factory-floor environments with wide temperature swings and electrical noise. IC Role / Device Role / Timing Role: Non-volatile boot memory providing deterministic 55 ns instruction fetch timing to ensure real-time scan-cycle consistency. Use Value: Eliminates reliance on slow serial EEPROM or volatile RAM + battery backup - guarantees immediate, repeatable startup after power loss without initialization delay. |
Use Scenario: Holding immutable BIOS or bootloader code in legacy 8-bit microcontroller systems (e.g., Z80, 8051) deployed in medical instrumentation or point-of-sale terminals. IC Role / Device Role / Timing Role: Primary read-only instruction store mapped to CPU reset vector; accessed via standard address/data bus with CE/OE handshaking. Use Value: Provides guaranteed data retention >10 years and immunity to accidental overwrite - critical for certified devices where firmware integrity is regulatory-mandated. |
| Automotive Instrument Cluster Calibration Data | Telecom Line Card Configuration Memory |
Use Scenario: Storing calibrated analog trim values and display lookup tables in automotive instrument clusters rated for -40°C to +125°C operation. IC Role / Device Role / Timing Role: OTP parameter store accessed during cluster power-up; read once at initialization using same 5V bus as MCU. Use Value: Avoids costly EEPROM endurance management and wear-leveling firmware - simplifies qualification for AEC-Q100 Grade 2 compliance. |
Use Scenario: Holding FPGA configuration bitstreams and port mapping tables in carrier-grade TDM line cards where field updates are rare but absolute reliability is mandatory. IC Role / Device Role / Timing Role: Static configuration ROM interfaced to FPGA configuration controller; read sequentially during power-on reset. Use Value: Delivers 256K-byte capacity in compact PLCC package - saves board area versus multiple smaller EPROMs while maintaining proven radiation-tolerant process. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar OTP EPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM27C256B-120DC | 256K × 8 OTP EPROM, 120 ns access, 32-pin PDIP, 5V only, no integrated ID code | Lacks Rapid™ programming and product ID - requires manual algorithm selection in programmers | Lower-cost option where programming speed and auto-identification are non-critical |
| MX27C256A-12PC | 256K × 8 OTP EPROM, 120 ns access, 32-pin PDIP, 5V ±5%, no VPP pin (internal charge pump) | No external VPP requirement - simplifies programming hardware but removes voltage-level flexibility | Preferred when eliminating high-voltage programming circuitry reduces system BOM cost |
Compared with AM27C256B-120DC and MX27C256A-12PC, the AT27C020-55JC offers faster 55 ns access, integrated ID coding for automated programming, and explicit VPP control - making it optimal for high-throughput manufacturing and systems requiring guaranteed boot timing.
Availability
AT27C020-55JC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy embedded boot ROM, automotive instrument cluster calibration data, and telecom line card configuration memory requiring stable component supply and long-term obsolescence support.
Supply support for AT27C020-55JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, non-volatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT27C020-55JC belongs to Atmel's 27C-series OTP EPROM product line, designed specifically for reliable, high-speed firmware and configuration storage in cost-sensitive, high-volume embedded systems where data immutability and 5V compatibility are essential.
FAQ
What is the operating temperature range for the AT27C020-55JC?
The AT27C020-55JC is specified for commercial temperature operation from 0°C to 70°C. This range is confirmed in the Ordering Information table, where the "-55JC" suffix denotes the PLCC package and commercial grade. It is not rated for industrial (-40°C to +85°C) or automotive (-40°C to +125°C) ranges - those require suffixes like "-55JI" or "-55JA".
Does the AT27C020-55JC require a high-voltage supply for normal read operation?
No, the AT27C020-55JC operates from a single 5V ±10% supply during read mode. VPP (13.0 V ±0.25 V) is required only during programming and must be disconnected or held at 5V during system operation. The datasheet explicitly states that VPP may be tied to VCC except during programming - confirming no high-voltage rail is needed for runtime functionality.
How many address pins does the AT27C020-55JC have, and what is their function?
The AT27C020-55JC has 18 address pins: A0 through A17. These pins decode the full 256K-byte memory space (218 = 262,144 addresses × 8 bits = 2,097,152 bits). Each unique combination selects one byte for read or program access - no external address multiplexing or latching is required due to the parallel architecture.
Can the AT27C020-55JC be reprogrammed in-system?
No, the AT27C020-55JC is a one-time programmable (OTP) EPROM. Once programmed, its contents cannot be erased or rewritten. Programming requires external 13 V VPP and specialized equipment; there is no UV erasure window or electrical erase capability. The "OTP" designation in the device description and features section confirms permanent data retention after initial programming.
What is the purpose of the PGM pin on the AT27C020-55JC?
The PGM pin on the AT27C020-55JC is an active-low programming strobe used exclusively during write cycles. When asserted low with VPP = 13 V, it triggers the internal 100 µs programming pulse per byte. In read mode, PGM is ignored - the datasheet specifies "X" (don't care) for PGM during read and standby modes, confirming it has no functional role outside programming.
AT27C020-55JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EPROM
- Technology:
- EPROM - OTP
- Memory Size:
- 2Mbit
- Memory Organization:
- 256K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- -
- Access Time:
- 55 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT27C020-55JC FAQ
1.How can I place an order for AT27C020-55JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT27C020-55JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT27C020-55JC reliable?
The price and inventory of AT27C020-55JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT27C020-55JC is usually 5 days.
3.What payment methods are accepted for AT27C020-55JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT27C020-55JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT27C020-55JC?
AT27C020-55JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT27C020-55JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT27C020-55JC?
For technical support, including AT27C020-55JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT27C020-55JC requirements.
6.How does Aetrix verify that AT27C020-55JC is sourced from the original manufacturer or authorized distributors?
All AT27C020-55JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT27C020-55JC meets industry standards.
7.What is the process for return or replacement of AT27C020-55JC?
All AT27C020-55JC units undergo pre-shipment inspection (PSI). If there is an issue with AT27C020-55JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT27C020-55JC part is unused and in its original packaging.
Return procedure for AT27C020-55JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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