Microchip Technology AT28BV256-20TI
- Part No.:
- AT28BV256-20TI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28BV256-20TI.pdf
- Description:
- IC EEPROM 256KBIT PAR 28TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,202
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Product details
Overview
AT28BV256-20TI from Atmel is a 256 Kbit (32K × 8) parallel EEPROM operating from a single 2.7V–3.6V supply, featuring 200 ns read access time, 10 ms maximum page write cycle, JEDEC-standard byte-wide pinout, and industrial temperature range (−40°C to +85°C). It supports hardware/software data protection and DATA polling for write completion detection in embedded control and firmware storage applications.
For engineers reviewing the AT28BV256-20TI datasheet, AT28BV256-20TI pinout, AT28BV256-20TI application, or AT28BV256-20TI equivalent, key selection considerations include its battery-voltage operation, 64-byte page write capability, CMOS standby current of 20 µA, endurance of 10,000 cycles, and compatibility with static RAM-like interface timing.
Technical Context
The AT28BV256-20TI implements a parallel EEPROM architecture with internal 64-byte page latching and autonomous internal control timer for self-timed writes. Its dual-line chip enable (CE) and output enable (OE) logic enables bus contention avoidance in multi-device systems.
It supports three write modes: byte write, page write (1–64 bytes within same A6–A14 page), and software-protected programming requiring a 3-byte unlock sequence. End-of-write detection is implemented via DATA polling on I/O7 or toggle-bit monitoring on I/O6.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8 bits); sufficient for firmware boot code, calibration tables, or configuration storage in resource-constrained systems. |
| Read Access Time | 200 ns max; enables direct replacement of SRAM in legacy designs without timing redesign. |
| Page Write Cycle | 10 ms max; allows efficient bulk updates of up to 64 bytes per write operation, reducing host CPU overhead. |
| Supply Voltage | 2.7V–3.6V; compatible with 3.3V logic systems and battery-backed operation without level shifting. |
| Standby Current | 20 µA (CMOS); supports ultra-low-power retention in always-on industrial controllers. |
| Endurance | 10,000 write/erase cycles; suitable for infrequent but critical parameter logging or field-upgradeable configuration. |
| Data Retention | 10 years at 85°C; ensures long-term reliability in unattended industrial deployments. |
Pinout & Package
AT28BV256-20TI is packaged in a 28-lead Plastic Thin Small Outline Package (TSOP), compliant with JEDEC MO-183, measuring 8 mm × 13.4 mm with 0.55 mm lead pitch. Pin 1 identifier is marked by a beveled corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus selecting one of 32,768 memory locations; A6–A14 define 64-byte page boundaries for page write mode. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 provides DATA polling feedback; I/O6 provides toggle-bit status during write cycles. |
| CE | Chip Enable | Active-low device select; when high, forces outputs to high-impedance and inhibits all writes regardless of OE/WE state. |
| OE | Output Enable | Active-low read control; used with CE to prevent bus contention; must be high during write operations. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write; combined with CE for robust noise immunity (15 ns pulse rejection). |
| VCC | Power Supply | 2.7V–3.6V supply input; includes internal power-on delay (~10 ms) to prevent inadvertent writes during power ramp. |
| GND | Ground Reference | Signal and power return path; decoupling capacitor required near VCC pin for stable read/write operation. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection | Requires 3-byte unlock sequence (5555H/2AAAH/A0H) before each write; prevents corruption during power-up/down or system instability. |
| Hardware Write Inhibit | Automatic VCC power-on delay, CE/OE/WE logic gating, and 15 ns noise filtering eliminate need for external reset supervision. |
| Page Write Mode | Internal 64-byte latch allows burst loading of up to 64 bytes with automatic internal programming-no external timing control needed. |
| DATA Polling & Toggle Bit | Dual end-of-write detection: I/O7 returns complemented data until complete; I/O6 toggles during write-enables polling without dedicated status lines. |
| Device Identification Area | 64-byte reserved EEPROM block (7FC0H–7FFFH) accessible via 12V on A9; supports unique device serialization or firmware version tracking. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via parallel bus during boot and runtime reconfiguration; 200 ns read latency meets deterministic scan-cycle timing. Use Value: Enables field-upgradable settings without firmware reflashing; 10,000-cycle endurance supports decades of maintenance cycles under industrial temperature stress (−40°C to +85°C). | Use Scenario: Retaining sensor calibration coefficients, patient history flags, and safety-critical operational limits in portable diagnostic equipment with battery backup. IC Role / Device Role / Timing Role: Battery-voltage EEPROM providing tamper-resistant storage for FDA-regulated calibration data; accessed only during startup or service mode. Use Value: 2.7V–3.6V operation ensures reliable retention during brownout conditions; software protection prevents accidental overwrites during low-power states. |
| Automotive Body Control Module | Telecom Equipment Bootloader Storage |
Use Scenario: Holding seat/mirror position presets, lighting profiles, and door lock configurations in automotive body control units exposed to wide thermal cycling. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to microcontroller's external memory bus; operates across −40°C to +85°C without derating. Use Value: 10-year data retention at 85°C guarantees parameter integrity over vehicle lifetime; JEDEC pinout ensures drop-in compatibility with legacy designs. | Use Scenario: Storing bootloader images and secure boot keys in carrier-grade networking hardware where firmware integrity is enforced by cryptographic verification. IC Role / Device Role / Timing Role: Firmware nonvolatile storage accessed during cold boot; 200 ns read speed avoids boot-time bottlenecks in high-throughput packet processors. Use Value: Page write capability enables fast field updates of bootloader patches; hardware/software protection prevents unauthorized modification of boot code. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W256F | 256 Kbit, 2.7V–3.6V, 200 ns access, but requires 12V VPP for programming; no software protection. | Lacks integrated software data protection and automatic page write; needs external high-voltage generator. | Choose when legacy 12V programming infrastructure exists and software protection is not required. |
| Microchip 25LC256 | 256 Kbit SPI EEPROM, 2.5V–5.5V, 5 MHz interface; no parallel bus, lower pin count, but slower effective throughput than 200 ns parallel reads. | Serial interface reduces PCB routing complexity but increases CPU overhead for bulk reads/writes. | Prefer for space-constrained designs where SPI is already used and timing-critical parallel access is unnecessary. |
Compared with ST M28W256F and Microchip 25LC256, the AT28BV256-20TI delivers true parallel bus performance with zero external voltage requirements and built-in dual-layer data protection-making it optimal for deterministic, low-overhead firmware and configuration storage in industrial and automotive systems.
Availability
AT28BV256-20TI is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and telecom bootloader storage requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AT28BV256-20TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a U.S.-based semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for industrial, automotive, and communications markets.
The AT28BV256 product line was designed for battery-voltage, high-reliability parallel EEPROM applications demanding fast read access, robust write protection, and extended data retention in harsh environments.
FAQ
What is the operating voltage range of the AT28BV256-20TI?
The AT28BV256-20TI operates from a single 2.7V to 3.6V supply, making it compatible with standard 3.3V logic systems and enabling direct integration into battery-powered devices without voltage translation. This range is strictly enforced-operation below 2.7V may result in unreliable writes or data corruption, and exceeding 3.6V violates absolute maximum ratings.
Does the AT28BV256-20TI require an external high-voltage supply for programming?
No, the AT28BV256-20TI does not require an external high-voltage supply such as 12V VPP. All write operations-including byte, page, and software-protected writes-are performed using only the standard 2.7V–3.6V VCC supply. The optional 12V on A9 is exclusively for accessing the 64-byte device identification area (7FC0H–7FFFH), not for main array programming.
How does DATA polling work on the AT28BV256-20TI?
During a write cycle, reading the last written byte from the AT28BV256-20TI causes I/O7 to output the complement of that data. Once the internal write completes, I/O7 returns the true value. This allows the host processor to poll I/O7 without halting other operations-no additional status pins or timers are needed. Polling can begin immediately after initiating the write.
What package types are available for the AT28BV256-20TI?
The AT28BV256-20TI is specifically offered in the 28-lead Plastic Thin Small Outline Package (TSOP), designated as package code "T" in Atmel's ordering nomenclature. Other variants like AT28BV256-20JI use PLCC or PDIP, but the -TI suffix confirms TSOP packaging with industrial temperature rating (−40°C to +85°C).
Can the AT28BV256-20TI be used as a direct replacement for standard SRAM in existing designs?
Yes-the AT28BV256-20TI uses a JEDEC-approved byte-wide pinout and behaves electrically like a Static RAM during read cycles: CE and OE low with WE high asserts data on I/O0–I/O7. However, write cycles require proper timing and software protection activation, so SRAM replacement requires firmware adaptation to manage writes-not just pin-for-pin substitution.
AT28BV256-20TI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28BV256-20TI FAQ
1.How can I place an order for AT28BV256-20TI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28BV256-20TI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28BV256-20TI reliable?
The price and inventory of AT28BV256-20TI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28BV256-20TI is usually 5 days.
3.What payment methods are accepted for AT28BV256-20TI?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28BV256-20TI?
AT28BV256-20TI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28BV256-20TI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28BV256-20TI?
For technical support, including AT28BV256-20TI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28BV256-20TI requirements.
6.How does Aetrix verify that AT28BV256-20TI is sourced from the original manufacturer or authorized distributors?
All AT28BV256-20TI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28BV256-20TI meets industry standards.
7.What is the process for return or replacement of AT28BV256-20TI?
All AT28BV256-20TI units undergo pre-shipment inspection (PSI). If there is an issue with AT28BV256-20TI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28BV256-20TI part is unused and in its original packaging.
Return procedure for AT28BV256-20TI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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