Microchip Technology AT28BV64B-20JC
- Part No.:
- AT28BV64B-20JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28BV64B-20JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28BV64B-20JC from Atmel (now Microchip) is a 64 Kbit (8K × 8) parallel EEPROM with battery-voltage operation (2.7V–3.6V), 200 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling, and toggle-bit write completion detection, and is commonly used in industrial control systems for firmware parameter storage and calibration data retention.
For engineers reviewing the AT28BV64B-20JC datasheet, AT28BV64B-20JC pinout, AT28BV64B-20JC application, or AT28BV64B-20JC equivalent, key selection considerations include JEDEC byte-wide pin compatibility, 100,000 write endurance, 10-year data retention, CMOS standby current (20 µA), and support for 32-lead PLCC packaging at commercial temperature range (0°C to 70°C).
Technical Context
The AT28BV64B-20JC implements a static RAM-like interface with dual-line chip enable (CE) and output enable (OE) control, enabling flexible bus contention management. Its internal 64-byte page register latches addresses and data during page writes, decoupling the host bus for concurrent operations.
Write completion is verified via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle-bit monitoring-both usable at any point during the internal 10 ms max write cycle. Software Data Protection (SDP) requires a three-byte command sequence (AAh/55h/A0h) before each write, preventing corruption during power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable parallel EEPROM |
| Read Access Time | 200 ns maximum - enables direct replacement of SRAM in legacy 8-bit microcontroller systems |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic and battery-backed operation without level shifting |
| Active Current | 15 mA typical - low enough for continuous-read applications in power-constrained embedded nodes |
| Standby Current | 20 µA (CMOS) - supports long-term data retention in always-on industrial monitoring devices |
| Write Endurance | 100,000 cycles - sufficient for field-updatable configuration storage in programmable logic controllers |
| Data Retention | 10 years at 85°C - validated for use in sealed industrial enclosures without active thermal management |
Pinout & Package
AT28BV64B-20JC is supplied in a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016, Variation AE. Pins 1 and 17 are No Connect (NC). The device uses a standard JEDEC byte-wide parallel interface with address (A0–A12), data (I/O0–I/O7), and control (CE, OE, WE) pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | True 8-bit parallel interface - no external transceivers needed; supports simultaneous read/write verification via DATA polling on I/O7 |
| CE | Chip Enable | Active-low global enable; must be low with OE low and WE high for read access; used with WE for byte/page write initiation |
| OE | Output Enable | Active-low output control; when high, forces I/O lines to high-impedance - essential for bus sharing in multi-peripheral systems |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE for robust noise-immune write timing (15 ns filter) |
| VCC / GND | Power Supply | Single 2.7–3.6 V supply; internal VCC power-on delay (10 ms) prevents spurious writes during power ramp-up |
| NC (Pins 1, 17) | No Connect | Physically present but unconnected internally - must remain floating or tied to GND per PLCC mechanical requirements |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Operation | Writes up to 64 bytes in one internal cycle (≤10 ms), reducing host CPU overhead vs. sequential byte writes |
| Software Data Protection (SDP) | Three-step unlock sequence (AAh/55h/A0h) required before every write - eliminates unintended reprogramming during brown-out or reset |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection: I/O7 returns complement until done; I/O6 toggles until final state - no timer polling needed |
| Extra 64-Byte ID Area | Dedicated user-accessible memory block (7FC0H–7FFFH) enabled by 12 V on A9 - supports unique device serialization or firmware version tagging |
| JEDEC Byte-Wide Pinout | Pin-compatible with industry-standard 28-pin and 32-pin parallel EEPROM families - simplifies board-level migration and second-sourcing |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing runtime-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile parameter register accessed via 8-bit parallel bus during boot and runtime; retains values across AC power loss and cold restarts. Use Value: Enables field technicians to update machine behavior without firmware reflashing; 100,000-cycle endurance supports decades of recalibration events. |
Use Scenario: Holding sensor offset/gain coefficients, patient-specific therapy profiles, and regulatory audit logs in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage element interfaced directly to microcontroller's external memory bus; isolated from main application code space. Use Value: Meets IEC 62304 Class C data integrity requirements; software protection prevents accidental overwrite during battery-swapping or ESD events. |
| Telecom Line Card Firmware Patching | Automotive Body Control Module Settings |
|
Use Scenario: Storing hot-fix patches and feature-enabling bits for legacy telecom line cards where FPGA or DSP firmware cannot be updated in-field. IC Role / Device Role / Timing Role: Parallel-bootloader adjunct memory mapped into CPU address space; accessed only during initialization or maintenance mode. Use Value: Eliminates need for costly board respins; 200 ns access allows patch loading within tight boot-time budgets (<50 ms). |
Use Scenario: Retaining seat/mirror position memory, lighting preferences, and door lock behavior across ignition cycles in automotive body control modules (BCMs). IC Role / Device Role / Timing Role: Low-voltage EEPROM operating from vehicle battery (9–16 V via LDO); withstands cold-crank voltage dips to 6 V without data corruption. Use Value: 2.7 V minimum VCC and 20 µA standby current ensure reliable operation during extended parking; green (Pb/halide-free) packaging meets automotive RoHS compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-20JF1 | Real-time clock + 2 KB NV SRAM integrated; no page write; slower 350 ns access; wider 4.5–5.5 V range | Used where time-stamped logging is required; not suitable for high-speed parameter updates or battery-only operation | Select when RTC functionality is mandatory and voltage margin >3.6 V is available |
| Microchip 25LC640-I/P | 64 Kbit SPI EEPROM; 5 MHz interface; 5 ms write cycle; 5 V tolerant; no parallel bus or SDP | Preferred for new designs with limited PCB real estate and existing SPI infrastructure; lacks JEDEC pinout compatibility | Select for cost-sensitive, space-constrained designs where serial interface suffices and legacy pin compatibility is not required |
Compared with AT28BV64B-20JC, the ST M48T02-20JF1 adds RTC capability but sacrifices speed, low-voltage operation, and page-write efficiency; the 25LC640-I/P reduces footprint and pin count but requires protocol stack integration and loses deterministic 200 ns read latency.
Availability
AT28BV64B-20JC is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom infrastructure, and automotive body electronics requiring stable component supply and long-lifecycle support.
Supply support for AT28BV64B-20JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28BV64B belongs to Atmel's battery-voltage parallel EEPROM product line, designed specifically for legacy 8-bit system upgrades, industrial equipment with wide input voltage tolerance, and applications demanding JEDEC-standard pin compatibility and robust data integrity.
FAQ
What is the operating temperature range for the AT28BV64B-20JC?
The AT28BV64B-20JC is rated for commercial temperature operation from 0°C to 70°C. This is confirmed in the Ordering Information section (23.1), where "JC" suffix denotes the 32-lead PLCC package in the commercial grade. Industrial-grade variants (e.g., AT28BV64B-20JI) extend to –40°C to +85°C, but the -20JC variant does not support that range.
Does the AT28BV64B-20JC support page write, and what is the maximum page size?
Yes, the AT28BV64B-20JC supports page write with a maximum size of 64 bytes per internal programming cycle. This is explicitly stated in the Features list and detailed in Section 4.3 ("Page Write"), where it notes that all bytes must reside on the same page defined by A6–A12, and the internal control timer completes the operation in ≤10 ms.
How does software data protection (SDP) work on the AT28BV64B-20JC?
AT28BV64B-20JC requires a mandatory three-byte unlock sequence (AAh to address 1555h, 55h to address 0AAAh, then A0h to address 1555h) before any byte or page write. This SDP mechanism prevents inadvertent writes during power-up/down or noise events. The sequence must be repeated before each write operation, and failure to execute it results in no data being written - only a dummy write cycle timing out.
Can the AT28BV64B-20JC be used with a 3.3 V microcontroller without level shifters?
Yes, the AT28BV64B-20JC operates natively from 2.7 V to 3.6 V and specifies VIH = 2.0 V and VOL = 0.45 V (IOL = 1.6 mA), making it fully compatible with standard 3.3 V CMOS logic levels. Its JEDEC byte-wide pinout and TTL-compatible inputs eliminate the need for external level-shifting circuitry in 3.3 V system designs.
What package type is used for the AT28BV64B-20JC, and are there NC pins?
The AT28BV64B-20JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package (ordering code "32J"). Per the Pin Configurations diagram (Section 2.2), pins 1 and 17 are designated "Don't Connect" (DC/NC) - they are physically present but unconnected internally and must remain unconnected on the PCB.
AT28BV64B-20JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28BV64B-20JC FAQ
1.How can I place an order for AT28BV64B-20JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28BV64B-20JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28BV64B-20JC reliable?
The price and inventory of AT28BV64B-20JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28BV64B-20JC is usually 5 days.
3.What payment methods are accepted for AT28BV64B-20JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28BV64B-20JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28BV64B-20JC?
AT28BV64B-20JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28BV64B-20JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28BV64B-20JC?
For technical support, including AT28BV64B-20JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28BV64B-20JC requirements.
6.How does Aetrix verify that AT28BV64B-20JC is sourced from the original manufacturer or authorized distributors?
All AT28BV64B-20JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28BV64B-20JC meets industry standards.
7.What is the process for return or replacement of AT28BV64B-20JC?
All AT28BV64B-20JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28BV64B-20JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28BV64B-20JC part is unused and in its original packaging.
Return procedure for AT28BV64B-20JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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