Microchip Technology AT28BV64B-20JI
- Part No.:
- AT28BV64B-20JI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28BV64B-20JI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28BV64B-20JI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with battery-voltage operation (2.7V–3.6V), 200 ns read access time, 10 ms max page write cycle, and JEDEC-standard byte-wide pinout. It features hardware/software data protection, 100,000 write endurance, and industrial temperature support (−40°C to +85°C), used in embedded system configuration storage and firmware parameter retention.
For engineers reviewing the AT28BV64B-20JI datasheet, AT28BV64B-20JI pinout, AT28BV64B-20JI application, or AT28BV64B-20JI equivalent, key selection considerations include page-write capability (1–64 bytes), DATA polling/toggle-bit write completion detection, CMOS standby current (≤20 µA), and software data protection (SDP) command sequence requirements.
Technical Context
The AT28BV64B-20JI operates as a parallel-access EEPROM with static RAM-like read/write interface-no external timing components required. Its internal 64-byte page register latches address and data during page writes, enabling bus release for concurrent operations while an internal control timer manages programming.
Write completion is verified via dual methods: DATA polling on I/O7 (complement-to-data during write, true data upon completion) and toggle-bit behavior on I/O6. Hardware protection includes VCC power-on delay (~10 ms), noise filtering (<15 ns pulse rejection), and CE/OE/WE inhibit logic; software protection requires a three-byte command sequence (AAh/55h/A0h) before each write.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); supports full byte-addressable nonvolatile storage without refresh. |
| Read Access Time | 200 ns maximum; enables direct replacement of SRAM in legacy 8-bit bus systems with no wait-state insertion. |
| Page Write Cycle | 10 ms maximum; allows efficient bulk updates of up to 64 bytes per internal programming operation. |
| Supply Voltage | 2.7V–3.6V; compatible with 3.3V logic families and battery-backed industrial systems. |
| Endurance | 100,000 write/erase cycles; ensures long-term reliability in field-updatable configuration or calibration data storage. |
| Data Retention | 10 years at 85°C; guarantees persistent storage integrity across extended product lifecycles and thermal stress. |
| Standby Current | 20 µA typical CMOS standby; minimizes quiescent power in always-on or low-power sleep-mode applications. |
Pinout & Package
AT28BV64B-20JI uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package with standard JEDEC byte-wide pinout. Pin 1 is marked by corner cut; pins 1 and 17 are No Connect (NC). All inputs tolerate −0.6V to +6.25V; OE and A9 accept up to +13.5V for device identification mode.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 provides DATA polling output; I/O6 provides toggle-bit status during writes. |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; inhibits all writes when high. |
| OE | Output Enable | Active-low output control; places I/O pins in high-impedance state when high, preventing bus contention. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write when CE is low and OE is high. |
| VCC / GND | Power Supply | Single 2.7V–3.6V supply; GND referenced for all DC/AC specifications and noise immunity design. |
| NC | No Connect | Pins 1 and 17 are unconnected; must remain floating-no pull-up/down or routing required. |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Requires mandatory 3-byte unlock sequence (AAh→55h→A0h) before every write; prevents corruption during power transients. |
| Page Write Operation | Internal 64-byte latch frees address/data bus after initial byte load; enables interleaved host CPU operations during 10 ms programming. |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection: I/O7 returns complemented data until done; I/O6 toggles until final state stabilizes. |
| Industrial Temperature Range | Specified operation from −40°C to +85°C case temperature; validated for use in automotive under-hood, industrial PLC, and outdoor equipment. |
| Green Packaging Option | Pb/halide-free construction (JU variant); meets RoHS Directive 2011/65/EU without compromising JEDEC pin compatibility or AC timing. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing byte-level random access with guaranteed 10-year data retention at 85°C ambient. Use Value: Eliminates need for battery-backed SRAM; SDP prevents accidental overwrite during brown-out events common in industrial power grids. |
Use Scenario: Holding sensor calibration coefficients, patient-specific therapy settings, and regulatory audit logs in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, low-power EEPROM interfaced directly to microcontroller's 8-bit parallel bus for deterministic read/write latency. Use Value: 20 µA standby current extends battery life; 100,000-cycle endurance supports frequent recalibration without wear-out risk. |
| Automotive Body Control Module | Networking Equipment Boot Parameters |
Use Scenario: Retaining window position memory, mirror angle presets, and lighting profiles in vehicle body control units operating across −40°C to +85°C. IC Role / Device Role / Timing Role: JEDEC-compliant parallel EEPROM with industrial temp grade and hardware write-inhibit logic for ECU safety-critical data. Use Value: VCC power-on delay and noise filtering prevent spurious writes during ignition cycling; page write reduces firmware update time vs. byte-by-byte. |
Use Scenario: Storing MAC addresses, PHY initialization sequences, and fail-safe boot images in enterprise switches and routers with hot-swap capability. IC Role / Device Role / Timing Role: Directly mapped into microprocessor address space as boot ROM shadow; accessed via standard 8-bit bus timing. Use Value: 200 ns read access avoids wait states in MIPS/ARM-based network processors; DATA polling enables precise firmware update synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-20MH1 | Real-time clock + 2 KB NV SRAM integrated; requires external crystal; no page write; 10 µA standby. | RTC-critical systems needing time-stamped logging; not suitable for pure configuration storage without RTC overhead. | Select only if RTC functionality is required; otherwise, AT28BV64B-20JI offers higher density and faster page writes. |
| Microchip 25LC640-I/P | Serial SPI interface (not parallel); 64 Kbit; 5 ms write cycle; 5V-tolerant; no SDP or toggle-bit detection. | Space-constrained designs using SPI buses; incompatible with existing 8-bit parallel address/data layouts. | Choose only for new SPI-based designs; AT28BV64B-20JI maintains legacy parallel bus compatibility and richer write-status feedback. |
Compared with ST M48T02-20MH1 and Microchip 25LC640-I/P, the AT28BV64B-20JI delivers native parallel bus integration, deterministic 200 ns reads, dual write-completion signaling, and software/hardware data protection-making it optimal for retrofitting or maintaining legacy 8-bit microcontroller systems requiring robust, high-density EEPROM.
Availability
AT28BV64B-20JI is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, automotive body control module parameter backup, networking equipment boot parameter management, and embedded system firmware update staging requiring stable component supply and long-lifecycle support.
Supply support for AT28BV64B-20JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs, with a legacy of high-reliability industrial-grade products.
The AT28BV64B series was designed for embedded systems requiring pin-compatible, drop-in replacement of older EPROMs and battery-backed SRAMs-emphasizing data integrity, low-voltage operation, and simplified board-level integration without external timing circuitry.
FAQ
What is the maximum page write size supported by the AT28BV64B-20JI?
The AT28BV64B-20JI supports page write operations of 1 to 64 bytes per internal programming cycle. All bytes must reside within the same 64-byte page, defined by address bits A6–A12. Each successive byte must be loaded within 100 µs of the prior one; exceeding this interval triggers automatic programming initiation. This capability significantly reduces firmware update time compared to byte-by-byte writes.
Does the AT28BV64B-20JI require external circuitry for write protection?
No, the AT28BV64B-20JI incorporates both hardware and software write protection. Hardware protection includes VCC power-on delay (~10 ms), noise filtering on WE/CE inputs (<15 ns rejection), and write inhibition when CE is high, OE is low, or WE is high. Software Data Protection (SDP) mandates a three-byte unlock sequence (AAh→55h→A0h) before any write-eliminating need for external lock bits or discrete logic.
How is write completion detected on the AT28BV64B-20JI?
Write completion on the AT28BV64B-20JI is confirmed using two independent methods: DATA polling on I/O7 (returns complement of written data until complete, then true data) and toggle-bit monitoring on I/O6 (toggles between 0/1 during programming, stabilizes upon completion). Both methods operate asynchronously and can be polled at any time during the write cycle-no fixed timeout required.
What package type does the AT28BV64B-20JI use, and what are its key mechanical features?
The AT28BV64B-20JI uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package (JEDEC MS-016, Variation AE). Key features include gull-wing leads with 1.27 mm pitch, 13.4 mm × 13.4 mm body, 1.20 mm max height, and coplanarity ≤0.102 mm. Pins 1 and 17 are No Connect; pin 1 is identified by corner cut. The package supports reflow soldering and meets Pb/halide-free requirements.
Can the AT28BV64B-20JI be used in systems powered by a single 3.3V supply?
Yes, the AT28BV64B-20JI is fully specified for 2.7V to 3.6V operation, making it compatible with standard 3.3V logic supplies. Its active current is 15 mA at 5 MHz, standby current ≤20 µA, and input thresholds (VIL ≤0.6V, VIH ≥2.0V) align with 3.3V CMOS levels. No level-shifting or voltage regulation is needed for direct interface with 3.3V microcontrollers or FPGAs.
AT28BV64B-20JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28BV64B-20JI FAQ
1.How can I place an order for AT28BV64B-20JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28BV64B-20JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28BV64B-20JI reliable?
The price and inventory of AT28BV64B-20JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28BV64B-20JI is usually 5 days.
3.What payment methods are accepted for AT28BV64B-20JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28BV64B-20JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28BV64B-20JI?
AT28BV64B-20JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28BV64B-20JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28BV64B-20JI?
For technical support, including AT28BV64B-20JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28BV64B-20JI requirements.
6.How does Aetrix verify that AT28BV64B-20JI is sourced from the original manufacturer or authorized distributors?
All AT28BV64B-20JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28BV64B-20JI meets industry standards.
7.What is the process for return or replacement of AT28BV64B-20JI?
All AT28BV64B-20JI units undergo pre-shipment inspection (PSI). If there is an issue with AT28BV64B-20JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28BV64B-20JI part is unused and in its original packaging.
Return procedure for AT28BV64B-20JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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