My Inquiry
My Account
Microchip Technology AT28BV64B-20JU
- Part No.:
- AT28BV64B-20JU
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28BV64B-20JU.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:165
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
The AT28BV64B-20JU from Microchip Technology (formerly Atmel) is a 64K-bit (8K × 8) parallel EEPROM with battery-voltage operation, JEDEC-standard byte-wide pinout, and software/hardware data protection. It delivers 200 ns read access time, 10 ms maximum page write cycle time, 15 mA active current, and operates across -40°C to +85°C for industrial embedded control and firmware storage.
For engineers reviewing the AT28BV64B-20JU datasheet, AT28BV64B-20JU pinout, AT28BV64B-20JU application, or AT28BV64B-20JU equivalent, key selection criteria include its 2.7–3.6 V single-supply operation, 64-byte page write capability, DATA polling and toggle bit write completion detection, and green PLCC-32 packaging with 12 V device identification support.
Technical Context
The AT28BV64B-20JU functions as a drop-in static RAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on WE or CE low pulse with OE high. Its internal 64-byte page register latches address and data, freeing the bus during autonomous internal programming timed by an on-chip control timer.
Write operations require a mandatory three-byte Software Data Protection (SDP) command sequence (0xAA→0x55→0xA0 at addresses 0x1555/0x0AAA/0x1555) before any byte or page write. Device identification uses A9 raised to 12 V ± 0.5 V to access an additional 64-byte user EEPROM region at 0x0000–0x003F.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable parallel EEPROM |
| Read Access Time | 200 ns - enables direct replacement of SRAM in legacy 8-bit microcontroller systems without wait-state insertion |
| Page Write Cycle | ≤10 ms - supports burst programming of up to 64 bytes per internal cycle, reducing firmware update latency |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic domains and battery-backed operation |
| Endurance | 100,000 write/erase cycles - sufficient for field-upgradable configuration storage in industrial controllers |
| Data Retention | 10 years at 85°C - ensures long-term reliability in unattended embedded deployments |
| Standby Current | ≤50 µA - minimizes power draw in always-on monitoring systems during idle periods |
Pinout & Package
AT28BV64B-20JU is supplied in a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016, Variation AE, with lead coplanarity ≤0.102 mm and green (Pb/Halide-free) construction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; I/O7 provides DATA polling output; I/O6 provides toggle bit status |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; used with WE to initiate byte/page writes |
| OE | Output Enable | Active-low output control; high during write cycles to place outputs in high-impedance state |
| WE | Write Enable | Active-low write strobe; falling edge latches address; rising edge latches data; controls SDP command timing |
| VCC / GND | Power Supply | Single 2.7–3.6 V supply; decoupling required near pins 17 (VCC) and 32 (GND) |
| A9 (with 12 V) | Device ID Enable | Applying 12.0 V ± 0.5 V to A9 enables access to dedicated 64-byte device identification EEPROM space |
| Pins 1 & 17 | No Connect | Physically present but internally unconnected; must remain floating or tied to GND per design guidelines |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Ensures mechanical and electrical compatibility with legacy 28-pin and 32-pin parallel memory sockets and PCB footprints |
| 64-byte Page Write | Reduces firmware update time by >60× versus byte-write mode; eliminates external address sequencing logic |
| DATA Polling & Toggle Bit | Enables real-time write completion detection without fixed delays or external timers, simplifying host firmware |
| Software Data Protection (SDP) | Prevents accidental writes during power transitions via mandatory 3-byte unlock sequence, eliminating need for hardware write-protect lines |
| 12 V Device Identification | Provides secure, factory-programmable or field-configurable device serialization using standard address/data bus |
Applications
| Industrial PLC Configuration Storage | Legacy 8-bit Microcontroller Firmware Backup |
|---|---|
Use Scenario: Storing calibrated sensor offsets, I/O mapping tables, and runtime parameters in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during boot and runtime; retains data through 100,000+ power cycles. Use Value: Eliminates reliance on external battery-backed SRAM while maintaining 200 ns read speed for deterministic scan-cycle timing. | Use Scenario: Providing firmware recovery storage for Z80, 8051, or HC11-based embedded systems where main Flash lacks endurance or field update capability. IC Role / Device Role / Timing Role: Parallel-bootable code/data repository mapped into CPU address space; supports in-system reprogramming via page writes. Use Value: Enables safe over-the-air or local firmware updates with verified write completion (via I/O7 polling), avoiding corruption during brown-out events. |
| Medical Device Calibration Data | Telecom Line Card Parameter Tables |
Use Scenario: Holding calibration coefficients, usage counters, and safety-critical operational logs in Class II medical instruments requiring 10-year data retention. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store accessed only during initialization or service mode; protected by SDP and voltage-level gating. Use Value: Meets IEC 62304 data integrity requirements via hardware-enforced write inhibition and 100,000-cycle endurance for recalibration events. | Use Scenario: Storing channel gain settings, filter coefficients, and fault history in carrier-grade DSLAM line cards exposed to wide temperature swings. IC Role / Device Role / Timing Role: Industrial-temperature EEPROM interfaced directly to DSP or FPGA configuration bus; supports hot-swap parameter reloads. Use Value: Guarantees reliable operation from -40°C to +85°C with <50 µA standby current, minimizing thermal drift impact on analog front-end tuning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-20MH1 | Integrated lithium battery + real-time clock; 64K × 8 NV SRAM architecture; no page write; 70 ns access | Requires battery management; suited for RTC + memory combo use cases; not pin-compatible | Select when time-stamped logging or battery-backed volatile memory is required alongside nonvolatile storage |
| ON Semiconductor CAT28C64B-20L | Same 64K × 8 organization and JEDEC pinout; 25 mA active current; 100 µA standby; no SDP or 12 V ID | Lacks software write protection and device ID area; requires external hardware write-enable control | Choose for cost-sensitive designs where simplified write control and absence of SDP are acceptable trade-offs |
Compared with ST M48T02-20MH1 and CAT28C64B-20L, the AT28BV64B-20JU uniquely combines page write acceleration, dual write-completion detection (polling + toggle), and secure device identification-all within a green PLCC-32 package rated for industrial temperatures-making it optimal for firmware-critical, update-robust embedded systems.
Availability
AT28BV64B-20JU is available at Aetrix Electronics and suitable for industrial PLCs, legacy microcontroller firmware backup, medical device calibration storage, and telecom line card parameter tables requiring stable component supply and long-lifecycle support.
Supply support for AT28BV64B-20JU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT28BV64B family.
The AT28BV64B series was designed specifically for industrial and embedded applications requiring robust, parallel-interface EEPROM with enhanced write protection, page programming efficiency, and extended temperature operation-replacing older NMOS EEPROMs in mission-critical systems.
FAQ
What is the required voltage on A9 to access the device identification EEPROM in the AT28BV64B-20JU?
The AT28BV64B-20JU requires 12.0 V ± 0.5 V applied to pin A9 to enable access to the dedicated 64-byte device identification EEPROM space located at addresses 0x0000–0x003F. This high-voltage enable prevents accidental writes during normal 3.3 V operation and is specified in Section 4.7 and Table 7 of the datasheet. The AT28BV64B-20JU's device ID feature supports secure serialization without requiring additional ICs or firmware overhead.
Does the AT28BV64B-20JU support true simultaneous read-while-write operation?
No, the AT28BV64B-20JU does not support concurrent read and write operations. During any write cycle-including byte or page writes-the device enters a busy state where read attempts return either complemented data (on I/O7 for polling) or toggling values (on I/O6), not valid memory contents. Valid reads resume only after write completion is confirmed via DATA polling or toggle bit stabilization. This behavior is explicitly defined in Sections 4.4 and 4.5 of the AT28BV64B-20JU datasheet.
What is the minimum time between successive bytes in a page write operation for the AT28BV64B-20JU?
The AT28BV64B-20JU requires each successive byte in a page write to be loaded within 100 µs (tBLC) of the previous byte, as specified in Section 4.3 and Table 16. Exceeding this interval causes the device to terminate data loading and begin internal programming immediately. This timing constraint ensures reliable page buffer management and is critical for achieving the guaranteed 10 ms maximum page write cycle time. The AT28BV64B-20JU's tBLC limit applies regardless of whether the page is fully loaded or partially written.
Is the AT28BV64B-20JU pin-compatible with standard 28-pin SOIC EEPROMs like the AT28C64B?
No, the AT28BV64B-20JU is not pin-compatible with 28-pin SOIC EEPROMs such as the AT28C64B. The AT28BV64B-20JU uses a 32-lead PLCC package (ordering code suffix 'JU') with distinct pin assignments-including NC pins at positions 1 and 17-and differs in supply voltage range (2.7–3.6 V vs. 4.5–5.5 V), access timing, and feature set. While both share JEDEC byte-wide functional pinouts, physical layout, pin count, and voltage tolerance prevent direct socket substitution. Always verify footprint and signal routing against the AT28BV64B-20JU PLCC drawing (24.1).
How does the Software Data Protection (SDP) mechanism work in the AT28BV64B-20JU?
The AT28BV64B-20JU implements Software Data Protection (SDP) as a mandatory three-byte unlock sequence: first write 0xAA to address 0x1555, then 0x55 to address 0x0AAA, then 0xA0 to address 0x1555. Only after this exact sequence is completed can subsequent byte or page writes proceed. Attempts without SDP trigger internal timers but write no data. This mechanism is detailed in Section 4.6.2 and Figure 17 of the AT28BV64B-20JU datasheet and applies to every write operation, including the AT28BV64B-20JU's device identification region.
AT28BV64B-20JU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28BV64B-20JU FAQ
1.How can I place an order for AT28BV64B-20JU through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28BV64B-20JU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28BV64B-20JU reliable?
The price and inventory of AT28BV64B-20JU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28BV64B-20JU is usually 5 days.
3.What payment methods are accepted for AT28BV64B-20JU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28BV64B-20JU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28BV64B-20JU?
AT28BV64B-20JU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28BV64B-20JU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28BV64B-20JU?
For technical support, including AT28BV64B-20JU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28BV64B-20JU requirements.
6.How does Aetrix verify that AT28BV64B-20JU is sourced from the original manufacturer or authorized distributors?
All AT28BV64B-20JU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28BV64B-20JU meets industry standards.
7.What is the process for return or replacement of AT28BV64B-20JU?
All AT28BV64B-20JU units undergo pre-shipment inspection (PSI). If there is an issue with AT28BV64B-20JU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28BV64B-20JU part is unused and in its original packaging.
Return procedure for AT28BV64B-20JU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28BV64B-20JU Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
