Microchip Technology AT28BV64B-20TI
- Part No.:
- AT28BV64B-20TI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28BV64B-20TI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28TSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28BV64B-20TI from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with battery-voltage operation, JEDEC-standard byte-wide pinout, and integrated software data protection. It delivers 200 ns read access time, 10 ms max page write cycle, and operates across -40°C to +85°C industrial temperature range using a single 2.7V–3.6V supply. It is used in embedded systems for firmware storage, calibration data retention, and configuration parameter backup.
For engineers reviewing the AT28BV64B-20TI datasheet, AT28BV64B-20TI pinout, AT28BV64B-20TI application, or AT28BV64B-20TI equivalent, key selection criteria include its 64-byte page write capability, DATA polling/toggle bit write completion detection, hardware/software write protection, CMOS standby current of 20 µA, and compatibility with static RAM-like interface timing.
Technical Context
The AT28BV64B-20TI implements a parallel EEPROM architecture with internal address and data latching for up to 64-byte page writes, eliminating external address/data bus hold requirements during programming. Its dual write detection mechanism-DATA polling on I/O7 and toggle bit on I/O6-enables reliable host-side write status monitoring without dedicated status pins.
It integrates both hardware-level protections (VCC power-on delay, noise filtering on WE/CE, write inhibit via control pin states) and software data protection (SDP), requiring a three-byte command sequence (0xAA, 0x55, 0xA0) before any write operation. The device also includes 64 bytes of dedicated identification memory accessible at 7FC0H–7FFFH using 12 V on A9.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8), organized as byte-addressable parallel EEPROM |
| Read Access Time | 200 ns - enables direct replacement of SRAM in legacy 8-bit microcontroller systems |
| Page Write Cycle | ≤10 ms - supports efficient bulk parameter updates without full chip erase |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems and battery-backed operation |
| Standby Current | 20 µA - minimizes power draw in always-on industrial control modules |
| Endurance | 100,000 write/erase cycles - suitable for field-updatable calibration tables |
| Data Retention | 10 years at 85°C - ensures long-term reliability in unattended equipment |
Pinout & Package
AT28BV64B-20TI is supplied in a 28-lead Thin Small Outline Package (TSOP, Type I, 8 × 13.4 mm), compliant with JEDEC MO-183. Pin 1 identifier is marked by a beveled corner; pins 1 and 17 are no-connect (NC) in PLCC variants but not applicable here - TSOP pinout follows JEDEC byte-wide standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; I/O7 provides DATA polling output; I/O6 provides toggle bit status |
| CE | Chip Enable | Active-low chip select; must be low with OE low and WE high for read; controls write initiation when combined with WE |
| OE | Output Enable | Active-low output control; places I/O pins in high-impedance state when high to prevent bus contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address; rising edge latches data; used with CE for dual-control write safety |
| VCC, GND | Power Supply | Single 2.7–3.6 V supply; GND referenced for all I/O and control signals |
| NC | No Connect | Pin 1 (TSOP top view) is NC - must remain unconnected per datasheet; not tied to ground or voltage |
Key Features
| Feature | Design Value |
|---|---|
| Software Data Protection (SDP) | Requires 3-byte unlock sequence (0xAA→0x55→0xA0) before every write - prevents corruption during power transitions |
| 64-byte Page Write | Internal latching allows sequential loading of 1–64 bytes within 100 µs intervals - reduces host CPU overhead vs. byte-by-byte writes |
| DATA Polling & Toggle Bit | Dual asynchronous write-complete detection on I/O7 and I/O6 - eliminates need for fixed delays or external timers |
| Industrial Temperature Range | -40°C to +85°C case operating range - qualified for deployment in motor drives, PLCs, and outdoor metering |
| Green Packaging Option | Pb/Halide-free TSOP package - meets RoHS Directive 2011/65/EU without derating or performance trade-offs |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via 8-bit parallel bus during boot and runtime reconfiguration. Use Value: Enables field updates without firmware reflashing; 100,000-cycle endurance supports decades of recalibration events. | Use Scenario: Retaining sensor offset/gain coefficients and patient-specific therapy settings in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Battery-backed parameter vault with deterministic 200 ns read latency for real-time correction lookups. Use Value: 10-year data retention at 85°C ensures accuracy compliance over full product lifecycle without periodic refresh. |
| Automotive Body Control Module (BCM) | Telecom Line Card Settings |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and door lock configurations in automotive BCMs. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced to 8-bit MCU via GPIO-mapped address/data bus; accessed during wake-up initialization. Use Value: 2.7–3.6 V operation tolerates automotive battery transients; SDP prevents spurious writes during ignition cycling. | Use Scenario: Holding port enable/disable states, gain settings, and fault history logs in carrier-grade DSLAM line cards. IC Role / Device Role / Timing Role: System-critical nonvolatile storage accessed during hot-swap insertion and firmware upgrade sequences. Use Value: Page write and DATA polling allow atomic multi-byte updates without service interruption or data corruption risk. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECT | 64 Mbit (8M × 8), 120 ns access, 3.3 V only, no software data protection | Higher density for firmware storage; lacks SDP and page write - requires external write gating logic | Select when >64 Kbit capacity is required and host can manage write timing externally |
| ON Semiconductor CAT28C64B | 64 Kbit, 200 ns access, 4.5–5.5 V supply, no SDP, no toggle bit | Legacy 5 V system compatibility; lacks modern low-voltage operation and dual-status detection | Select only for 5 V designs where voltage margin and write safety are managed at board level |
Compared with ST M28W640ECT and CAT28C64B, the AT28BV64B-20TI uniquely combines 2.7–3.6 V operation, integrated software/hardware write protection, and dual-status detection in a JEDEC-standard 28-pin TSOP - making it optimal for space-constrained, low-power industrial upgrades.
Availability
AT28BV64B-20TI is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, automotive body control modules, and telecom line cards requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT28BV64B-20TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel memory products. The company specializes in microcontrollers, analog, and nonvolatile memory solutions for industrial, automotive, and consumer markets.
The AT28BV64B-20TI belongs to Atmel's battery-voltage parallel EEPROM product line, designed specifically for reliable, low-power, pin-compatible replacement of older EPROM and EEPROM devices in legacy 8-bit systems with minimal redesign effort.
FAQ
What is the maximum page write size supported by the AT28BV64B-20TI?
The AT28BV64B-20TI supports a maximum page write size of 64 bytes. This is enabled by an internal 64-byte page register that latches addresses and data sequentially within a 100 µs window (tBLC). All bytes written in a single page operation must reside on the same page, defined by A6–A12 address bits. The AT28BV64B-20TI does not support partial-page or cross-page writes - exceeding tBLC or changing A6–A12 mid-sequence terminates the load and initiates internal programming.
Does the AT28BV64B-20TI require a 12 V supply for normal operation?
No, the AT28BV64B-20TI operates exclusively from a 2.7 V to 3.6 V supply during standard read/write cycles. A 12 V ± 0.5 V supply on pin A9 is required only for accessing the dedicated 64-byte device identification memory (7FC0H–7FFFH); this is a one-time or infrequent operation and must be isolated from the main VCC rail. All core EEPROM functions - including page write, DATA polling, and SDP - function fully at 3.3 V without high-voltage injection.
How does software data protection (SDP) work on the AT28BV64B-20TI?
Software data protection on the AT28BV64B-20TI requires a precise three-byte unlock sequence before each write: first write 0xAA to address 0x5555, then 0x55 to address 0x2AAA, then 0xA0 to address 0x5555. Only after this sequence is completed will the next write to any address initiate actual programming. The AT28BV64B-20TI ignores writes without the sequence - though internal timers still activate, temporarily disabling reads as polling operations for tWC duration.
Can the AT28BV64B-20TI be used as a drop-in replacement for the AT28C64B?
No, the AT28BV64B-20TI is not a drop-in replacement for the AT28C64B. While both are 64 Kbit parallel EEPROMs with JEDEC pinouts, the AT28C64B requires 4.5–5.5 V operation and lacks software data protection, page write, and DATA polling. The AT28BV64B-20TI's 2.7–3.6 V supply range, SDP command sequence, and 64-byte page buffer necessitate firmware and power design changes - it is a functional upgrade, not a pin-and-code compatible substitute.
What is the purpose of the toggle bit on I/O6 in the AT28BV64B-20TI?
The toggle bit on I/O6 provides a secondary, asynchronous method to detect write completion in the AT28BV64B-20TI. During active programming, successive reads cause I/O6 to alternate between high and low states; once the write finishes, I/O6 stabilizes and outputs valid data. Unlike DATA polling on I/O7, which returns complemented data until completion, the toggle bit requires no data comparison - simplifying host firmware logic. Both mechanisms are fully supported in the AT28BV64B-20TI and may be used interchangeably.
AT28BV64B-20TI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28BV64B-20TI FAQ
1.How can I place an order for AT28BV64B-20TI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28BV64B-20TI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28BV64B-20TI reliable?
The price and inventory of AT28BV64B-20TI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28BV64B-20TI is usually 5 days.
3.What payment methods are accepted for AT28BV64B-20TI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28BV64B-20TI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28BV64B-20TI?
AT28BV64B-20TI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28BV64B-20TI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28BV64B-20TI?
For technical support, including AT28BV64B-20TI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28BV64B-20TI requirements.
6.How does Aetrix verify that AT28BV64B-20TI is sourced from the original manufacturer or authorized distributors?
All AT28BV64B-20TI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28BV64B-20TI meets industry standards.
7.What is the process for return or replacement of AT28BV64B-20TI?
All AT28BV64B-20TI units undergo pre-shipment inspection (PSI). If there is an issue with AT28BV64B-20TI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28BV64B-20TI part is unused and in its original packaging.
Return procedure for AT28BV64B-20TI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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