Microchip Technology AT28C010-12FM/883
- Part No.:
- AT28C010-12FM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CFlatPack
- Datasheet:
-
AT28C010-12FM/883.pdf
- Description:
- IC EEPROM 1MBIT PAR 32FLATPACK
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C010-12FM/883 from Microchip Technology is a military-grade 1-Mbit (131,072 × 8) paged parallel EEPROM with 120 ns read access time, single 5V ±10% supply operation, and JEDEC-approved byte-wide pinout. It supports page write cycles of up to 128 bytes in ≤10 ms and delivers 300 µA CMOS standby current for low-power embedded systems requiring nonvolatile storage in harsh environments.
For engineers reviewing the AT28C010-12FM/883 datasheet, AT28C010-12FM/883 pinout, AT28C010-12FM/883 application, or AT28C010-12FM/883 equivalent, this device serves as a drop-in replacement for legacy parallel EEPROMs in avionics control modules, missile guidance firmware storage, radiation-tolerant telemetry recorders, and secure boot memory where MIL-STD-883 compliance and 10-year data retention are mandatory.
Technical Context
The AT28C010-12FM/883 implements a paged architecture with an internal 128-byte latch and autonomous control timer, enabling simultaneous write of 1–128 bytes without external timing circuitry. Its dual-line chip enable (CE) and output enable (OE) logic prevents bus contention during read operations, while hardware write inhibition-via VCC sense (3.8 V threshold), 5 ms power-on delay, and noise filtering (<15 ns)-ensures immunity to spurious writes during power transients.
Data integrity is maintained through DATA Polling (I/O7 complement feedback) and Toggle Bit (I/O6 toggling) mechanisms for precise end-of-write detection. The device includes 128 bytes of dedicated identification EEPROM accessible at 1FF80H–1FFFFH using A9 = 12 V ±0.5 V, and supports optional software data protection via three-byte command sequences (AAh/55h/A0h for enable; AAh/55h/80h/AAh/20h for disable).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 131,072 × 8 bits (1 Mbit); enables full firmware image storage for small microcontrollers without external address multiplexing. |
| Read Access Time | 120 ns max; supports direct interface to 8-bit microprocessors operating at ≤8 MHz without wait states. |
| Page Write Cycle | ≤10 ms; reduces firmware update latency by writing 128 bytes in one atomic operation instead of 128 individual byte writes. |
| Supply Voltage | 5 V ±10%; compatible with standard TTL/CMOS logic rails and eliminates need for auxiliary voltage regulators. |
| Standby Current | 300 µA (CMOS); extends battery life in always-on military subsystems such as GPS receivers and inertial measurement units. |
| Endurance | 10,000 write/erase cycles; sufficient for field-upgradable mission-critical configuration tables updated monthly over 8+ years. |
| Data Retention | 10 years at +125°C; validated for long-term deployment in sealed avionics enclosures without thermal derating. |
Pinout & Package
AT28C010-12FM/883 is supplied in a 32-lead CERDIP package (MIL-STD-1835 D-16 Config A), measuring 42.70 mm × 15.50 mm × 4.1 mm, with hermetically sealed ceramic construction and gold-plated leads rated for -55°C to +125°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 131,072-word addressing; A7–A16 define page boundaries for 128-byte page writes. |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit parallel interface compatible with Z80, 8051, and 68K families; I/O7 provides DATA Polling status, I/O6 provides Toggle Bit status. |
| CE | Chip Enable | Active-low global select; must be held low for read/write access; high-Z output state when deasserted to prevent bus contention. |
| OE | Output Enable | Active-low output gate; decouples data bus during address setup or write cycles to avoid signal conflicts on shared buses. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE and OE controls all write modes (byte/page/chip erase). |
| VCC | Power Supply | +5 V ±10% input; internally regulated for stable core voltage; triggers hardware write inhibit below 3.8 V. |
| GND | Ground Reference | Signal and power return path; requires low-inductance connection to minimize noise coupling into sensitive EEPROM cells. |
| NC (Pins 1 & 30) | No Connect | Unbonded terminals; must remain unconnected per MIL-STD-883 test requirements and reliability validation. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-Wide Pinout | Direct compatibility with legacy 27C256/27C512 socket layouts and PCB footprints, eliminating redesign for obsolescence replacement. |
| Hardware Write Inhibition | VCC sense, 5 ms power-on delay, and 15 ns noise filtering prevent accidental writes during brown-out, reset, or EMI events in flight-critical systems. |
| Software Data Protection | User-configurable lock via 3-byte command sequence (AAh/55h/A0h); protects entire array without hardware modification or fuse programming. |
| 128-Byte Identification Area | Dedicated EEPROM space at 1FF80H–1FFFFH, accessible with 12 V on A9, used for serialization, calibration data, or firmware version tracking. |
| MIL-STD-883 Compliance | Qualified per Method 5005 (Steady-State Life), 5007 (Temperature Cycling), and 5011 (Burn-In); certified for Class B (space-level) applications. |
Applications
| Avionics Flight Control Memory | Missile Guidance Firmware Storage |
|---|---|
|
Use Scenario: Storing real-time pitch/yaw/roll trim coefficients and sensor calibration tables in fly-by-wire flight computers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up initialization and runtime parameter updates via CAN bus. Use Value: 120 ns read access ensures immediate coefficient loading at system boot; 10,000-cycle endurance supports field recalibration every 3 months over 8+ years. |
Use Scenario: Holding encrypted guidance algorithms and target acquisition parameters in solid-fuel tactical missiles. IC Role / Device Role / Timing Role: Secure boot memory storing signed firmware images verified before execution by onboard cryptographic engine. Use Value: Software data protection prevents tampering during pre-launch handling; 10-year data retention guarantees mission readiness after long-term storage. |
| Secure Telemetry Recorder | Radiation-Tolerant Sensor Node |
|
Use Scenario: Capturing post-event diagnostic logs (e.g., launch vibration, stage separation shock) in hardened black-box recorders. IC Role / Device Role / Timing Role: High-reliability data sink buffering sensor streams until safe transmission window opens. Use Value: Page write capability (≤10 ms) enables burst logging of 128-sample datasets without data loss; 300 µA standby current extends battery life to >120 days. |
Use Scenario: Storing radiation-hardened sensor calibration offsets and fault thresholds in satellite star trackers exposed to total ionizing dose (TID). IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory retaining critical settings across multiple power cycles and TID exposure events. Use Value: Hermetic CERDIP packaging and 10-year retention at +125°C ensure data integrity in geosynchronous orbit thermal vacuum environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15FM/883 | 150 ns read access time; identical pinout, endurance (10k cycles), and MIL-STD-883 screening. | Suitable for systems with relaxed timing budgets where 30 ns slower access does not impact CPU wait-state count. | Select when cost optimization is prioritized and system clock frequency is ≤6.6 MHz. |
| DS2502-E48+T&R | 1-Wire serial interface; 1 kbit capacity; no parallel bus or address pins; factory-programmed 48-bit ID. | Used for simple device authentication or calibration storage-not for firmware or high-bandwidth data logging. | Choose only for ultra-low-pin-count designs where serial interface suffices and memory density <1 kbit is acceptable. |
Compared with AT28C010-12FM/883, the -15FM/883 offers identical reliability and packaging but trades 30 ns speed for lower unit cost, while DS2502-E48+T&R sacrifices parallel bandwidth and density for minimal footprint and inherent security via 1-Wire authentication-making it unsuitable as a functional or pin-compatible substitute.
Availability
AT28C010-12FM/883 is available at Aetrix Electronics and suitable for avionics control systems, missile guidance electronics, secure telemetry recorders, and radiation-tolerant sensor nodes requiring stable component supply under extended temperature and radiation constraints.
Supply support for AT28C010-12FM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions, with ISO 9001-certified manufacturing and MIL-PRF-38535 QML-V qualification capabilities.
The AT28C010 product line delivers radiation-tolerant, high-reliability parallel EEPROMs designed specifically for defense, aerospace, and space applications where data integrity, long-term retention, and environmental survivability are non-negotiable.
FAQ
What is the maximum operating temperature range for the AT28C010-12FM/883?
The AT28C010-12FM/883 is qualified for operation from -55°C to +125°C per MIL-STD-883 Method 5005, with absolute maximum ratings extending to +125°C under bias and +150°C for storage. This range is validated for continuous use in sealed avionics enclosures and missile canisters exposed to extreme thermal cycling.
How does the AT28C010-12FM/883 detect completion of a page write cycle?
The AT28C010-12FM/883 supports two hardware-confirmed methods: DATA Polling (reading I/O7 returns complement of last written byte until completion, then true data) and Toggle Bit (I/O6 toggles between 0 and 1 during write, then stabilizes). Both operate without halting the host processor and are fully characterized per DS20006311A Section 5.14–5.17.
Is the AT28C010-12FM/883 pin-compatible with standard 27C256 EPROMs?
No-the AT28C010-12FM/883 uses a JEDEC-approved byte-wide pinout matching 27C512 EPROMs (32-pin DIP/CLCC/Flatpack), not 27C256 (28-pin). Pin mapping differs: AT28C010-12FM/883 has A16, two NC pins, and no OE/CE inversion; 27C256 lacks A16 and uses different control pin assignments.
What voltage is required to access the 128-byte identification area in the AT28C010-12FM/883?
The 128-byte identification EEPROM (addresses 1FF80H–1FFFFH) requires A9 to be driven to 12.0 V ±0.5 V, as specified in DS20006311A Section 5.10 and Figure 5-10. Standard 5 V operation accesses only the main 1-Mbit array; applying 12 V to A9 enables read/write to the ID sector without affecting main memory contents.
Does the AT28C010-12FM/883 support chip-erase functionality?
Yes-the AT28C010-12FM/883 supports optional software chip erase using a 6-byte command sequence (documented in DS20006311A Section 5.10), which erases the entire 1-Mbit array in one operation. This feature is independent of page write and requires no external high-voltage programming supply beyond the standard 5 V VCC and 12 V on A9 for ID sector access.
AT28C010-12FM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-FlatPack, Ceramic Bottom-Brazed
AT28C010-12FM/883 FAQ
1.How can I place an order for AT28C010-12FM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C010-12FM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C010-12FM/883 reliable?
The price and inventory of AT28C010-12FM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C010-12FM/883 is usually 5 days.
3.What payment methods are accepted for AT28C010-12FM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C010-12FM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C010-12FM/883?
AT28C010-12FM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C010-12FM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C010-12FM/883?
For technical support, including AT28C010-12FM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C010-12FM/883 requirements.
6.How does Aetrix verify that AT28C010-12FM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C010-12FM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C010-12FM/883 meets industry standards.
7.What is the process for return or replacement of AT28C010-12FM/883?
All AT28C010-12FM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C010-12FM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C010-12FM/883 part is unused and in its original packaging.
Return procedure for AT28C010-12FM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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