Microchip Technology AT28C010-12JI

Overview

AT28C010-12JI from Atmel is a 1-Mbit (128K × 8) paged parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns read access time, 10 ms maximum page write cycle, and industrial temperature range (–40°C to +85°C). It operates from a single 5V ±10% supply, supports hardware/software data protection, and is used in firmware storage, configuration memory, and boot code retention for embedded controllers.

For engineers reviewing the AT28C010-12JI datasheet, AT28C010-12JI pinout, AT28C010-12JI application, or AT28C010-12JI equivalent, key selection criteria include verified 128-byte page write capability, DATA polling and toggle-bit write completion detection, CMOS/TTL I/O compatibility, VCC sense-based hardware write inhibit, and PLCC-32 industrial-grade packaging.

Technical Context

The AT28C010-12JI implements a paged architecture with an internal 128-byte latch enabling simultaneous writes of 1–128 bytes per cycle. Its dual-line chip enable (CE) and output enable (OE) control allows SRAM-like read/write timing without external logic.

Write operations are validated via DATA polling on I/O7 or toggle-bit behavior on I/O6, both usable at any point during the internal 10 ms programming period. Hardware protection includes VCC sensing (<3.8 V inhibits write), 5 ms power-on delay, noise filtering (<15 ns pulses rejected), and CE/OE/WE state-dependent write inhibition.

Key Specifications

Pinout & Package

AT28C010-12JI is supplied in a 32-lead Plastic J-Leaded Chip Carrier (PLCC-32) package with JEDEC MS-016AE outline, lead pitch 1.27 mm, body size 11.4 × 11.4 mm, and pin 1 marked by index notch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Compared with AT28C010-12JI, AT28C010-12PI trades surface-mount robustness for through-hole compatibility, while AT28C010E-12JI delivers 10× endurance at identical timing and packaging - making it the only drop-in upgrade path for high-cycle applications.

Availability

AT28C010-12JI is available at Aetrix Electronics and suitable for industrial PLCs, legacy embedded boot systems, telecom line cards, and automated test equipment requiring stable component supply across long product lifecycles.

Supply support for AT28C010-12JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C010 product line was designed for pin-compatible replacement of EPROM and battery-backed SRAM in industrial and telecom systems requiring field-updatable, high-reliability nonvolatile storage.

FAQ

What is the maximum page write size supported by the AT28C010-12JI?

The AT28C010-12JI supports a maximum page write size of 128 bytes. This is enabled by its internal 128-byte latch, which accepts sequential data within a 150 µs window (tBLC) per byte. All bytes in a single page write must reside on the same 128-byte boundary defined by address bits A7–A16. The AT28C010-12JI does not support larger burst writes or sector-level erases - each page write is independent and self-timed to complete within 10 ms.

Does the AT28C010-12JI require a 12V programming voltage?

No, the AT28C010-12JI operates from a single 5V ±10% supply for all normal read and write operations. A 12V ±0.5V voltage is required only for accessing the optional 128-byte device identification area (addresses 1FF80H–1FFFFH) by raising pin A9 to 12V - this is not needed for standard memory operation. The AT28C010-12JI uses internal charge pumps for write/erase, eliminating external high-voltage circuitry during firmware or configuration updates.

How does hardware write protection function on the AT28C010-12JI?

Hardware write protection on the AT28C010-12JI operates through four concurrent mechanisms: (1) VCC sense - write is inhibited if VCC falls below ~3.8 V; (2) Power-on delay - a 5 ms internal timer blocks writes until VCC stabilizes; (3) Signal-state inhibition - holding CE high, OE low, or WE high prevents write initiation; and (4) Noise filtering - input pulses shorter than 15 ns on CE or WE are ignored. These features ensure the AT28C010-12JI remains immune to spurious writes during power transients or EMI events.

Can the AT28C010-12JI be used as a direct replacement for a 27C010 EPROM?

The AT28C010-12JI is pin-compatible with the 27C010 EPROM in PLCC-32, PDIP-32, and TSOP-32 packages and shares the same JEDEC byte-wide pinout. However, it is not a drop-in replacement because it requires active WE control (unlike EPROM's passive programming), supports page writes instead of byte-only writes, and has different timing (e.g., tACC = 120 ns vs. typical 250 ns for 27C010). The AT28C010-12JI replaces EPROMs only when the host system implements proper WE sequencing and write-completion polling.

What is the purpose of the DATA polling and toggle-bit functions in the AT28C010-12JI?

DATA polling and toggle-bit functions provide two independent, asynchronous methods to detect write completion in the AT28C010-12JI without halting the host processor. During a write, reading the last written byte returns its complement on I/O7 (DATA polling), while I/O6 toggles between 0 and 1 (toggle bit). Both signals stabilize once the internal 10 ms programming finishes. These features eliminate the need for fixed delays or external busy indicators - the AT28C010-12JI itself signals readiness, enabling efficient polling loops or interrupt-driven handling in real-time systems.