Microchip Technology AT28C010-15EM/883
- Part No.:
- AT28C010-15EM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28C010-15EM/883.pdf
- Description:
- IC EEPROM 1MBIT PARALLEL 32LCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C010-15EM/883 from Microchip Technology is a military-grade 1-Mbit (131,072 × 8) paged parallel EEPROM with 150 ns read access time, JEDEC-standard byte-wide pinout, and single 5V ±10% supply operation. It supports automatic 1–128-byte page writes with internal latching and timer control, and delivers 300 µA CMOS standby current for low-power embedded systems in aerospace and defense avionics.
For engineers reviewing the AT28C010-15EM/883 datasheet, AT28C010-15EM/883 pinout, AT28C010-15EM/883 application, or AT28C010-15EM/883 equivalent, key selection criteria include its MIL-STD-883 Class B qualification, 128-byte page register architecture, DATA Polling/Toggle Bit write completion detection, hardware/software data protection, and compatibility with legacy SRAM-based memory interfaces.
Technical Context
The AT28C010-15EM/883 implements a paged write architecture with an internal 128-byte latch that accepts sequential data within 150 µs intervals; address lines A7–A16 define the page boundary, while A0–A6 select bytes within the page. Its dual-line chip enable (CE) and output enable (OE) control enables bus contention avoidance in multiprocessor systems.
It features VCC-sense write inhibition below 3.8 V, 5 ms power-on delay before write enable, noise filtering on WE/CE inputs (<15 ns pulses rejected), and optional software data protection using a three-byte command sequence (AAh/55h/A0h) to lock writes across the full memory array.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Capacity | 131,072 × 8 bits (1 Mbit); supports direct replacement of 128K × 8 SRAM in legacy designs without external timing logic. |
| Read Access Time | 150 ns maximum; meets timing requirements for 6-MHz Z80, 8086, and MIL-STD-1750A bus cycles. |
| Page Write Cycle | 10 ms maximum; enables burst programming of up to 128 bytes per cycle, reducing firmware update latency vs. byte-by-byte writes. |
| Supply Voltage | 5 V ±10%; operates across full military temperature range (−55°C to +125°C) without derating. |
| Standby Current | 300 µA (CMOS mode); enables low-quiescent-power operation in always-on mission-critical subsystems. |
| Data Retention | 10 years minimum at +125°C; validated per MIL-STD-883 Method 1008 for long-term nonvolatile storage in sealed avionics enclosures. |
| Endurance | 10,000 write/erase cycles; sufficient for field-upgradable configuration tables and calibration data logging. |
Pinout & Package
AT28C010-15EM/883 is packaged in a 32-lead CLCC (Ceramic Leadless Chip Carrier) with 0.050" pitch, compliant with MIL-STD-1835 C-12. The package provides hermetic sealing, thermal stability, and radiation tolerance required for space-qualified and high-reliability defense applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus; A7–A16 define 128-byte page boundaries for page write operations. |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; supports DATA Polling on I/O7 and Toggle Bit detection on I/O6 during write cycles. |
| CE | Chip Enable | Active-low global device select; must be held low during read/write; enables bus sharing with other peripherals. |
| OE | Output Enable | Active-low output gate; allows high-impedance tri-state control independent of CE for shared data bus arbitration. |
| WE | Write Enable | Active-low write strobe; initiates byte or page write; combined with CE/OE logic to prevent accidental writes. |
| VCC | Power Supply | +5 V ±10% supply; internally monitored for voltage-level write inhibition and power-on delay sequencing. |
| GND | Ground Reference | Signal and power return; decoupling capacitor placement critical for noise immunity in high-speed read cycles. |
| NC | No Connect | Pins 1 and 30 are unconnected; must remain floating-no tie-high/tie-low or routing allowed. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-Wide Pinout | Direct drop-in replacement for industry-standard 27C512 EPROMs and 62256 SRAMs in existing PCB layouts. |
| Hardware Data Protection | VCC sense, 5 ms power-on delay, and noise-filtered WE/CE inputs eliminate need for external power-monitoring ICs. |
| Software Data Protection (SDP) | User-configurable lock via AAh/55h/A0h command sequence; prevents unintended writes during power transitions or reset glitches. |
| DATA Polling & Toggle Bit | Real-time write status feedback on I/O7 and I/O6 eliminates fixed-delay polling loops and reduces firmware overhead. |
| MIL-STD-883 Class B Qualification | Includes screening for thermal cycling, mechanical shock, vibration, and burn-in-certified for flight-critical subsystems. |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
|
Use Scenario: Storing real-time trim parameters, sensor calibration coefficients, and fail-safe control profiles in fly-by-wire flight computers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to MIL-STD-1553B host processor buses with SRAM-compatible timing. Use Value: 150 ns read access ensures deterministic response within 1553B command-response windows; 10-year data retention guarantees integrity across aircraft service life. |
Use Scenario: Holding encrypted channel maps, encryption keys, and operational mode settings in handheld and vehicular SINCGARS radios. IC Role / Device Role / Timing Role: Secure boot-time configuration store accessed during cold start; protected by SDP against RF-induced corruption. Use Value: Hardware write inhibit prevents key overwrite during EMI events; 300 µA standby current extends battery life in manpack radios. |
| Spacecraft Onboard Telemetry Buffer | Nuclear Power Plant Safety Logic Firmware |
|
Use Scenario: Capturing pre-failure telemetry snapshots and storing watchdog-triggered diagnostic logs in CubeSat attitude control units. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile buffer for time-critical event capture; operates across −55°C to +125°C orbital thermal swings. Use Value: Hermetic CLCC package and MIL-STD-883 screening ensure reliability in total ionizing dose (TID) environments up to 100 krad(Si). |
Use Scenario: Storing certified safety-critical firmware images and hardware interlock configurations in reactor protection systems. IC Role / Device Role / Timing Role: Qualified nonvolatile memory for IEC 61508 SIL-3 applications; write-protection enforced during power-up/down sequences. Use Value: Dual hardware/software protection prevents unauthorized firmware modification; 10,000-cycle endurance supports periodic safety audits and updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15DM/883 | Same die, 32-lead CERDIP package; larger footprint, through-hole mounting, higher thermal resistance. | Suitable for legacy board assemblies requiring socketed DIP replacement; not recommended for new surface-mount designs. | Select only if mechanical compatibility with existing CERDIP sockets is mandatory; CLCC offers superior thermal and vibration performance. |
| AT28C010-15FM/883 | Same die, 32-lead flatpack package; metal-ceramic construction, lower profile than CERDIP, but no hermetic seal. | Used in cost-sensitive defense electronics where MIL-STD-883 screening is required but hermeticity is not mandated. | Choose when weight and height constraints favor flatpack, and environmental sealing is handled at system level (e.g., conformal coating). |
Compared with AT28C010-15EM/883, the DM/883 variant trades surface-mount reliability for socket compatibility, while the FM/883 sacrifices hermeticity for reduced profile-neither matches the CLCC's balance of ruggedness, thermal performance, and modern assembly compatibility.
Availability
AT28C010-15EM/883 is available at Aetrix Electronics and suitable for avionics flight control systems, tactical radio configuration storage, and spacecraft telemetry buffering requiring stable component supply under extended lead times and obsolescence risk management.
Supply support for AT28C010-15EM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and aerospace markets.
The AT28C010 product line was designed to provide radiation-tolerant, high-reliability EEPROM alternatives to EPROM and battery-backed SRAM in mission-critical embedded systems requiring guaranteed data retention and write protection.
FAQ
What is the operating temperature range for the AT28C010-15EM/883?
The AT28C010-15EM/883 is qualified per MIL-STD-883 Class B with an operating temperature range of −55°C to +125°C. This specification is validated across all electrical parameters including read access time (150 ns max), write cycle time (10 ms max), and standby current (300 µA max), ensuring reliable operation in extreme environmental conditions encountered in aerospace and defense platforms.
How does the AT28C010-15EM/883 implement write protection?
The AT28C010-15EM/883 implements dual-layer write protection: hardware-level inhibition via VCC sensing (write disabled below 3.8 V), 5 ms power-on delay, and noise filtering on WE/CE inputs; plus software-level protection using a three-byte command sequence (AAh → 55h → A0h) to lock the entire memory array. Both mechanisms operate independently and are active simultaneously in the AT28C010-15EM/883.
Can the AT28C010-15EM/883 be used as a direct replacement for standard SRAMs?
Yes-the AT28C010-15EM/883 uses JEDEC-standard byte-wide pinout and SRAM-compatible read timing (150 ns access, CE/OE dual-control), enabling drop-in replacement for 128K × 8 SRAMs like the 62256 in legacy designs. However, write cycles require explicit software handling (page write, DATA Polling), unlike volatile SRAM's transparent write behavior.
What package type is used for the AT28C010-15EM/883?
The AT28C010-15EM/883 is supplied in a 32-lead CLCC (Ceramic Leadless Chip Carrier) package per MIL-STD-1835 C-12. This hermetically sealed, surface-mount package provides superior thermal conductivity, mechanical robustness, and radiation tolerance compared to CERDIP or flatpack variants-critical for high-reliability military and space applications.
Does the AT28C010-15EM/883 support page erase or only full-chip erase?
The AT28C010-15EM/883 supports only full-chip erase via a 6-byte software command sequence; it does not support sector or page erase. Erasure requires applying 12.0 V ± 0.5 V to A9 while executing the defined command, and is intended for factory reprogramming or complete configuration reset-not for field-level partial updates.
AT28C010-15EM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 150 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28C010-15EM/883 FAQ
1.How can I place an order for AT28C010-15EM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C010-15EM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C010-15EM/883 reliable?
The price and inventory of AT28C010-15EM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C010-15EM/883 is usually 5 days.
3.What payment methods are accepted for AT28C010-15EM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C010-15EM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C010-15EM/883?
AT28C010-15EM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C010-15EM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C010-15EM/883?
For technical support, including AT28C010-15EM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C010-15EM/883 requirements.
6.How does Aetrix verify that AT28C010-15EM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C010-15EM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C010-15EM/883 meets industry standards.
7.What is the process for return or replacement of AT28C010-15EM/883?
All AT28C010-15EM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C010-15EM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C010-15EM/883 part is unused and in its original packaging.
Return procedure for AT28C010-15EM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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