Microchip Technology AT28C010-15PC
- Part No.:
- AT28C010-15PC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28C010-15PC.pdf
- Description:
- IC EEPROM 1MBIT PARALLEL 32DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,443
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C010-15PC from Atmel is a 1-Mbit (128K × 8) paged parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, 10 ms maximum page write cycle, and CMOS/TTL-compatible I/O. It operates on single 5V ±10% supply and supports hardware/software data protection for embedded firmware storage in industrial control systems.
For engineers reviewing the AT28C010-15PC datasheet, AT28C010-15PC pinout, AT28C010-15PC application, or AT28C010-15PC equivalent, this page delivers verified timing specs, validated page-write behavior, confirmed JEDEC-compliant pin mapping, and real-world EEPROM replacement guidance for legacy system maintenance and BOM continuity planning.
Technical Context
The AT28C010-15PC implements a paged architecture with a 128-byte internal latching register, enabling simultaneous write of 1–128 bytes per cycle without external address/data bus hold. Its dual-line chip enable (CE) and output enable (OE) control eliminates bus contention during mixed read/write operations in microcontroller-based systems.
Write completion detection uses DATA POLLING on I/O7 (complement-to-data toggle) or TOGGLE BIT on I/O6, both functional during active programming. Hardware protection includes VCC sense (<3.8V inhibit), 5 ms power-on delay, and noise filtering (<15 ns pulse rejection) on WE/CE inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 Mbit (131,072 × 8), directly replaceable for 128K-byte firmware storage without address decoding changes |
| Read Access Time | 150 ns max - compatible with 6 MHz Z80, 8 MHz 8051, and 10 MHz 68000 bus timing |
| Page Write Cycle | 10 ms max - enables 128-byte firmware patch writes within tight system reset windows |
| Endurance | 10,000 write cycles - sufficient for field-upgradable boot code with <100 updates over product lifetime |
| Standby Current | 200 µA CMOS - supports low-power sleep modes in battery-backed industrial controllers |
| Supply Voltage | 5V ±10% - interoperable with legacy 5V logic families without level-shifting circuitry |
| Operating Temp | -40°C to +85°C - qualified for industrial PLC backplanes and motor drive control modules |
Pinout & Package
AT28C010-15PC is supplied in a 32-lead, 0.600" wide plastic dual inline package (PDIP), JEDEC MS-011 compliant, with 0.1" lead pitch and through-hole mounting.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus (A0 LSB to A16 MSB); A7–A16 define 128-byte page boundaries for write operations |
| CE | Chip Enable | Active-low device select; must be low for read/write; high forces high-impedance I/O and inhibits writes |
| OE | Output Enable | Active-low output control; used with CE to prevent bus contention during shared memory access |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming timer |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit parallel interface; I/O7 provides DATA POLLING status; I/O6 provides TOGGLE BIT status |
| GND / VCC | Power Terminals | Ground (Pin 16) and +5V supply (Pin 32); decoupling capacitor required within 1 cm of VCC pin |
| NC | No Connect | Pins 1, 31 (PDIP) are unconnected; must remain floating - no pull-up/down or routing allowed |
Key Features
| Feature | Design Value |
|---|---|
| Automatic Page Write | 128-byte internal latch frees address/data bus after initial byte load - enables background processing during 10 ms internal programming |
| DATA POLLING & TOGGLE BIT | Real-time write status via I/O7 complement or I/O6 toggle - eliminates need for fixed-delay polling loops in firmware |
| Hardware Write Protection | VCC sense + 5 ms power-on delay + noise filtering - prevents spurious writes during brown-out or EMI events |
| Software Data Protection (SDP) | User-enabled 3-byte command sequence (AAh/55h/A0h) - blocks accidental writes without hardware modification |
| Device Identification Area | 128 bytes at 1FF80H–1FFFFH accessible with A9 = 12V - supports unique serial number or calibration data storage |
Applications
| Industrial PLC Firmware Storage | Legacy Computer BIOS Backup |
|---|---|
|
Use Scenario: Storing configuration parameters and ladder logic firmware in programmable logic controllers operating in factory-floor environments with voltage fluctuations and EMI. IC Role / Device Role / Timing Role: Nonvolatile program memory holding boot code and user-defined control routines; accessed as SRAM-mapped peripheral with 150 ns read timing. Use Value: 200 µA standby current extends battery backup life; hardware write protection prevents corruption during power cycling; JEDEC pinout ensures drop-in replacement for aging AT28C256 designs. |
Use Scenario: Retaining BIOS settings and boot sector patches in vintage x86 systems (e.g., 486-based test equipment) where flash memory is unavailable or unsupported. IC Role / Device Role / Timing Role: Byte-addressable shadow ROM; replaces obsolete 27C512 EPROMs with in-system reprogrammability and no UV eraser requirement. Use Value: 10 ms page write allows full 128-byte BIOS update in under 15 ms; 5V-only operation avoids dual-supply complexity; software data protection prevents accidental CMOS RAM overwrite. |
| Medical Device Calibration Data | Automotive Body Control Module |
|
Use Scenario: Storing sensor calibration coefficients and safety-critical fault logs in Class II medical instruments requiring long-term data retention and tamper resistance. IC Role / Device Role / Timing Role: Secure nonvolatile parameter store; accessed during power-up initialization and runtime diagnostics using standard 8-bit parallel bus. Use Value: 10-year data retention meets IEC 62304 requirements; 12V-programmable ID area stores device-specific calibration keys; SDP prevents unauthorized firmware modification. |
Use Scenario: Holding door lock actuator profiles and lighting sequence tables in automotive body control units exposed to -40°C cold cranking and 85°C under-hood temperatures. IC Role / Device Role / Timing Role: Field-updatable configuration memory; integrated into CAN gateway subsystems for over-the-air parameter updates via diagnostic port. Use Value: Industrial temperature range (-40°C to +85°C) ensures reliability across thermal cycles; 128-byte page writes enable efficient partial table updates without full erase; CMOS/TTL compatibility simplifies interface to 80C51 derivatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-15JI | Same die, PLCC-32 package, industrial temp (-40°C to +85°C); identical timing and pinout | Requires surface-mount assembly; better thermal cycling performance but higher rework cost | Select when board space constraints favor PLCC or when extended thermal margin is required beyond PDIP limits |
| AT28C010E-15PC | Enhanced endurance (100K cycles vs. 10K); same 150 ns access, 10 ms write, PDIP-32 package | Supports frequent field updates (e.g., daily firmware patches); no change to PCB or timing margins | Choose for applications requiring >10K lifetime writes - such as remote telemetry gateways with weekly OTA updates |
Compared with AT28C010-15PC, the AT28C010-15JI offers identical electrical behavior in a surface-mount package for automated assembly, while AT28C010E-15PC doubles endurance without altering layout or firmware - making it ideal for systems needing frequent reprogramming without hardware redesign.
Availability
AT28C010-15PC is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy computer BIOS backup, and medical device calibration data retention requiring stable component supply across extended product lifecycles.
Supply support for AT28C010-15PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor innovator known for high-reliability nonvolatile memory and microcontroller solutions targeting industrial, automotive, and embedded markets.
The AT28C010 product line was designed specifically for drop-in replacement of UV-erasable EPROMs in legacy 8-bit and 16-bit systems, delivering in-system programmability, JEDEC pin compatibility, and robust data retention without requiring system-level redesign.
FAQ
What is the maximum page write size supported by the AT28C010-15PC?
The AT28C010-15PC supports up to 128 bytes per page write operation. This is enabled by its internal 128-byte latching register, which accepts sequential data within a 150 µs window (tBLC). All bytes must reside on the same page, defined by address bits A7–A16. The AT28C010-15PC does not require external address sequencing - the host only needs to maintain valid A0–A6 for byte selection within the page.
How does DATA POLLING work on the AT28C010-15PC during a write cycle?
During a write cycle, reading the last written byte from the AT28C010-15PC returns the complement of that data on I/O7 until programming completes. Once valid data appears on I/O7, the write is finished. This allows firmware to poll I/O7 without fixed delays - the AT28C010-15PC asserts true data only after internal timing (max 10 ms) and verification are complete.
Can the AT28C010-15PC be used as a direct replacement for the AT28C256 in existing designs?
No - the AT28C010-15PC is not a pin-compatible replacement for AT28C256. While both use 32-pin PDIP packages, AT28C256 has 16 address lines (A0–A15) and 256 Kbit density, whereas AT28C010-15PC requires A0–A16 (17 lines) and provides 1 Mbit. Address decoding, memory map size, and timing margins differ; redesign of address logic and firmware is required to migrate to AT28C010-15PC.
What is the purpose of the 12V signal on A9 for the AT28C010-15PC?
The 12V signal applied to A9 on the AT28C010-15PC enables access to the dedicated 128-byte device identification area (addresses 1FF80H–1FFFFH). This region is electrically isolated from main memory and supports independent read/write operations for serial numbers, calibration data, or manufacturing traceability - without affecting operational firmware stored elsewhere in the AT28C010-15PC array.
Does the AT28C010-15PC require external pull-up resistors on its I/O lines?
No - the AT28C010-15PC features TTL/CMOS-compatible outputs with active drive capability (VOH ≥ 2.4V at -400 µA, VOL ≤ 0.45V at 2.1 mA) and does not require external pull-ups for standard bus interfacing. Pull-ups may be needed only in specific cases like wired-OR configurations or open-collector emulation, but these are not inherent to AT28C010-15PC operation.
AT28C010-15PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 150 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 32-PDIP
AT28C010-15PC FAQ
1.How can I place an order for AT28C010-15PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C010-15PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C010-15PC reliable?
The price and inventory of AT28C010-15PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C010-15PC is usually 5 days.
3.What payment methods are accepted for AT28C010-15PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C010-15PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C010-15PC?
AT28C010-15PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C010-15PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C010-15PC?
For technical support, including AT28C010-15PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C010-15PC requirements.
6.How does Aetrix verify that AT28C010-15PC is sourced from the original manufacturer or authorized distributors?
All AT28C010-15PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C010-15PC meets industry standards.
7.What is the process for return or replacement of AT28C010-15PC?
All AT28C010-15PC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C010-15PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C010-15PC part is unused and in its original packaging.
Return procedure for AT28C010-15PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C010-15PC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

