Microchip Technology AT28C010-20FM/883
- Part No.:
- AT28C010-20FM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CFlatPack
- Datasheet:
-
AT28C010-20FM/883.pdf
- Description:
- IC EEPROM 1MBIT PAR 32FLATPACK
- Quantity:
- Payment:

- Shipping:

Inventory:1,358
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C010-20FM/883 from Microchip Technology is a military-grade 1-Mbit (131,072 × 8) paged parallel EEPROM with 120 ns read access time, JEDEC-approved byte-wide pinout, and single 5V ±10% supply operation. It supports page write cycles of up to 128 bytes in ≤10 ms and delivers 300 µA CMOS standby current for low-power embedded systems requiring nonvolatile storage in harsh environments.
For engineers reviewing the AT28C010-20FM/883 datasheet, AT28C010-20FM/883 pinout, AT28C010-20FM/883 application, or AT28C010-20FM/883 equivalent, this device serves as a drop-in replacement for legacy parallel EEPROMs in avionics, missile guidance, and spaceborne telemetry where extended temperature range (–55°C to +125°C), radiation-tolerant packaging, and hardware/software data protection are mandatory.
Technical Context
The AT28C010-20FM/883 implements a paged architecture with an internal 128-byte latch and autonomous control timer, enabling simultaneous latching of address and data before initiating self-timed internal programming. Its dual-line chip enable (CE) and output enable (OE) logic prevents bus contention during read operations.
It features DATA Polling on I/O7 and Toggle Bit detection on I/O6 for real-time end-of-write verification without external timing components. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and write-inhibit via CE/OE/WE states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 Mbit (131,072 × 8) - supports full memory map addressing without bank switching |
| Read Access Time | 200 ns max (AT28C010-20 grade) - compatible with 5 MHz bus timing in MIL-STD-1553 or ARINC-429 interface controllers |
| Page Write Cycle | ≤10 ms - enables burst writes of up to 128 bytes per cycle, reducing firmware overhead in configuration storage |
| Operating Temperature | –55°C to +125°C - qualified per MIL-PRF-38535 Class B for flight-critical subsystems |
| Supply Voltage | 5V ±10% - eliminates need for dedicated voltage regulators in legacy 5V military platforms |
| Standby Current | 300 µA CMOS - enables battery-backed operation for >10 years in unpowered storage mode |
| Endurance | 10,000 write/erase cycles - sufficient for field-updatable mission parameters in tactical radios |
| Data Retention | 10 years at +125°C - validated for long-term deployment in sealed avionics enclosures |
Pinout & Package
AT28C010-20FM/883 is supplied in a 32-lead flatpack package (MIL-STD-1835 32F outline), hermetically sealed with ceramic body and bottom-brazed construction. Pin 1 is marked by chamfered corner; pins are arranged in two parallel rows with 0.050" pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A16 | Address Inputs | 17-bit address bus supporting full 131,072-word decoding; A7–A16 define page boundaries for 128-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 provides DATA Polling status, I/O6 provides Toggle Bit confirmation |
| CE | Chip Enable | Active-low selection signal; must remain low ≥50 ns between reads to avoid data corruption |
| OE | Output Enable | Active-low output gating; used with CE for bus contention control in multi-device systems |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; high-to-low transitions initiate byte or page writes |
| VCC | Power Supply | +5V ±10% main supply; internally monitored for VCC sense protection below 3.8 V |
| GND | Ground Reference | Signal and power return; decoupling capacitor required within 0.5" of VCC/GND pins per MIL-STD-1537 |
| NC | No Connect | Pins 1 and 30 are unconnected; must be left floating or tied to GND per PCB layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-Wide Pinout | Direct compatibility with legacy 27C256/27C512 socket layouts and PCB footprints |
| Hardware Data Protection | VCC sense, 5 ms power-on delay, and noise filtering eliminate need for external reset supervisors |
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) enables selective write-enable without hardware modification |
| Page Write Architecture | 128-byte internal latch reduces host CPU intervention and bus occupancy during firmware updates |
| Device Identification Area | 128-byte reserved sector (1FF80H–1FFFFH) accessible via 12V A9 for unique unit serialization |
| MIL-PRF-38535 Class B Qualification | Full screening including burn-in, temperature cycling, and hermeticity testing per QML-V requirements |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
|
Use Scenario: Storing real-time trim calibration tables and sensor bias offsets in fly-by-wire flight computers operating across –55°C to +125°C. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing immediate read access at power-on without initialization delay. Use Value: 120 ns read access ensures synchronization with 5 MHz ARINC-429 bus clocks; 10,000-cycle endurance supports field recalibration every 500 flight hours. |
Use Scenario: Holding frequency hopping sequences and encryption keys in manpack radios subjected to shock, vibration, and thermal cycling. IC Role / Device Role / Timing Role: Secure parameter store with hardware/software write protection preventing accidental overwrites during RF transmission bursts. Use Value: 300 µA standby current extends battery life in standby mode; 12V-programmable ID area enables cryptographic key binding to hardware identity. |
| Missile Guidance System Boot ROM | Spacecraft Telemetry Logger |
|
Use Scenario: Hosting boot firmware and fault recovery routines in solid-fuel missile guidance units with zero tolerance for data corruption. IC Role / Device Role / Timing Role: Radiation-hardened nonvolatile memory executing deterministic startup sequence within 200 ns of power application. Use Value: MIL-PRF-38535 Class B qualification ensures survivability under neutron flux; page write capability reduces boot image update time to <10 ms. |
Use Scenario: Capturing housekeeping sensor data (voltage, temperature, pressure) during orbital insertion phases where power may be intermittent. IC Role / Device Role / Timing Role: Low-power logging buffer retaining data across brownout events using internal charge retention. Use Value: 10-year data retention at +125°C guarantees integrity during multi-year deep-space missions; DATA Polling allows precise write completion detection without polling overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C010-20JM/883 | 32-lead CERDIP package instead of flatpack; identical electrical specs and MIL-PRF-38535 Class B screening | Preferred for through-hole assembly or legacy CERDIP socket compatibility | Select when board layout requires vertical mounting or existing tooling supports CERDIP sockets |
| AT28C010-20EM/883 | 32-pad CLCC package; same timing, endurance, and temperature rating but different thermal profile and solder reflow requirements | Suitable for surface-mount designs requiring hermetic sealing and higher I/O density | Choose for new SMT designs where footprint size and thermal dissipation are prioritized over through-hole serviceability |
Compared with AT28C010-20FM/883, the JM variant offers identical functionality in a through-hole ceramic DIP for legacy repair, while the EM variant provides surface-mount compatibility with enhanced thermal performance-both retain full MIL-PRF-38535 Class B compliance and 120 ns read timing.
Availability
AT28C010-20FM/883 is available at Aetrix Electronics and suitable for avionics, missile guidance, and spacecraft telemetry requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for AT28C010-20FM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28C010 product line was designed specifically for military and space applications demanding radiation-tolerant, high-reliability parallel EEPROMs with extended temperature operation and robust data protection mechanisms.
FAQ
What is the maximum page write size supported by the AT28C010-20FM/883?
The AT28C010-20FM/883 supports page write operations of 1 to 128 bytes per cycle. All bytes must reside on the same 128-byte page defined by address bits A7–A16, and each successive byte must be loaded within 150 µs of the previous one. This architecture reduces firmware overhead and enables efficient bulk updates of configuration data in the AT28C010-20FM/883 without requiring external timing circuitry.
How does hardware data protection work in the AT28C010-20FM/883?
The AT28C010-20FM/883 implements four hardware protection mechanisms: VCC sense (write inhibited if supply drops below 3.8 V), 5 ms power-on delay before write enable, write-inhibit via CE/OE/WE logic states, and noise filtering rejecting pulses shorter than 15 ns on WE or CE. These features ensure the AT28C010-20FM/883 remains immune to spurious writes during power transients or EMI events in mission-critical systems.
Can the AT28C010-20FM/883 be used in place of older 27C256 EPROMs?
Yes-the AT28C010-20FM/883 uses a JEDEC-approved byte-wide pinout identical to 27C256, allowing direct PCB footprint replacement. Unlike UV-erasable EPROMs, the AT28C010-20FM/883 supports in-system electrical erasure and programming, eliminating the need for EPROM programmers or UV erasers while maintaining full read compatibility and timing alignment with legacy 5 MHz bus architectures.
What is the purpose of the 128-byte device identification area in the AT28C010-20FM/883?
The AT28C010-20FM/883 reserves 128 bytes (addresses 1FF80H–1FFFFH) for user-defined device identification. Access requires raising A9 to 12V ±0.5V, enabling secure serialization, cryptographic key binding, or calibration data storage independent of main memory. This area is electrically isolated and retains data for 10 years at +125°C, making it ideal for asset tracking in the AT28C010-20FM/883 deployed across defense platforms.
Does the AT28C010-20FM/883 support chip erase functionality?
Yes-the AT28C010-20FM/883 supports optional software chip erase using a 6-byte command sequence. When executed, this command erases the entire 1-Mbit array in a single operation. The erase function is distinct from page write and requires specific timing and voltage conditions per the datasheet. Chip erase capability simplifies field reprogramming of the AT28C010-20FM/883 without requiring specialized hardware tools.
AT28C010-20FM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-FlatPack, Ceramic Bottom-Brazed
AT28C010-20FM/883 FAQ
1.How can I place an order for AT28C010-20FM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C010-20FM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C010-20FM/883 reliable?
The price and inventory of AT28C010-20FM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C010-20FM/883 is usually 5 days.
3.What payment methods are accepted for AT28C010-20FM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C010-20FM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C010-20FM/883?
AT28C010-20FM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C010-20FM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C010-20FM/883?
For technical support, including AT28C010-20FM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C010-20FM/883 requirements.
6.How does Aetrix verify that AT28C010-20FM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C010-20FM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C010-20FM/883 meets industry standards.
7.What is the process for return or replacement of AT28C010-20FM/883?
All AT28C010-20FM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C010-20FM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C010-20FM/883 part is unused and in its original packaging.
Return procedure for AT28C010-20FM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C010-20FM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

