Microchip Technology AT28C010-20JI

Overview

AT28C010-20JI from Atmel is a 1-Mbit (128K × 8) paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 10 ms maximum page write cycle, and industrial temperature range (–40°C to +85°C). It operates on single 5V ±10% supply, supports hardware/software data protection, and is used in firmware storage, configuration memory, and boot code retention in embedded controllers.

For engineers reviewing the AT28C010-20JI datasheet, AT28C010-20JI pinout, AT28C010-20JI application, or AT28C010-20JI equivalent, key selection criteria include page-write capability (1–128 bytes), DATA polling/Toggle Bit for write completion detection, CMOS standby current (200 µA), VCC sense-based write inhibit, and PLCC-32 packaging compatibility with legacy socketed designs.

Technical Context

The AT28C010-20JI implements a paged architecture with a 128-byte internal page register, enabling simultaneous latching of up to 128 bytes before autonomous internal programming. Its dual-line chip enable (CE) and output enable (OE) control allows SRAM-like read/write timing without external logic.

Write operation relies on either hardware-level VCC sensing (<3.8 V inhibits writes) or software-controlled data protection (SDP) via three-byte command sequences. End-of-write detection is supported by DATA polling on I/O7 and Toggle Bit behavior on I/O6-both usable at any point during the write cycle.

Key Specifications

Pinout & Package

AT28C010-20JI is packaged in a 32-lead Plastic J-leaded Chip Carrier (PLCC-32), pin-compatible with JEDEC MS-016AE standard. Pin 1 is designated "Don't Connect" (DC) per manufacturer specification.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Compared with AT28C010-20JI, the AT28C010-20PI requires PCB layout change due to package form factor, while AT28C010E-20JI offers 10× endurance with full pin-and-function compatibility - making it the preferred upgrade path for future-proofing without hardware modification.

Availability

AT28C010-20JI is available at Aetrix Electronics and suitable for industrial PLCs, legacy embedded boot systems, and telecom line card calibration requiring stable component supply across extended product lifecycles.

Supply support for AT28C010-20JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for industrial and embedded markets.

The AT28C010 product line was designed as a direct SRAM/EPROM replacement for 8-bit systems needing in-system reprogrammability, low-power retention, and JEDEC-standard pin compatibility - targeting industrial control, instrumentation, and communications equipment.

FAQ

What is the maximum page write size supported by the AT28C010-20JI?

The AT28C010-20JI supports page write operations of 1 to 128 bytes per internal programming cycle. All bytes must reside within the same 128-byte page defined by address lines A7–A16, and successive bytes must be loaded within 150 µs of each other. This architecture reduces host processor overhead significantly compared to byte-by-byte writes, and the AT28C010-20JI's internal page register handles address/data latching autonomously after initiation.

Does the AT28C010-20JI require a 12V programming voltage?

No, the AT28C010-20JI operates exclusively from a single 5V ±10% supply for both read and write operations. The 12V requirement applies only to the optional device identification area (1FF80H–1FFFFH), which is accessed by raising A9 to 12V ±0.5V - this is not used during normal memory operation. All standard read, byte write, and page write functions of the AT28C010-20JI execute at 5V, simplifying power design and eliminating high-voltage charge pumps.

How does hardware write protection work on the AT28C010-20JI?

Hardware write protection on the AT28C010-20JI uses four mechanisms: (1) VCC sense - writes disabled if VCC drops below ~3.8 V; (2) Power-on delay - automatic 5 ms inhibition after VCC reaches threshold; (3) Signal-level inhibition - holding CE high, OE low, or WE high blocks writes; and (4) Noise filtering - pulses <15 ns on WE or CE are ignored. These features ensure the AT28C010-20JI remains immune to spurious writes during power transients or EMI events without software intervention.

Can the AT28C010-20JI be used as a direct replacement for standard SRAM?

Yes, the AT28C010-20JI is accessed like a Static RAM for reads and writes - CE and OE control enables SRAM-style bus interfacing without external timing logic. However, write cycles require 10 ms internal programming time, so the host must use DATA polling on I/O7 or Toggle Bit on I/O6 to detect completion before initiating subsequent accesses. Unlike SRAM, the AT28C010-20JI retains data without power, making it ideal for nonvolatile SRAM replacement where persistence is required.

What is the purpose of the extra 128 bytes in the AT28C010-20JI?

The AT28C010-20JI includes an additional 128-byte EEPROM sector located at addresses 1FF80H–1FFFFH, accessible only when A9 is raised to 12V ±0.5V. This area is intended for device-specific data such as serial numbers, manufacturing date codes, calibration constants, or firmware version stamps - providing traceability and customization without consuming main array space. It is electrically isolated from normal operation and does not affect the timing or reliability of the primary 128K × 8 memory array in the AT28C010-20JI.