Microchip Technology AT28C040-20BI
- Part No.:
- AT28C040-20BI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CDIP (0.600", 15.24mm)
- Datasheet:
-
AT28C040-20BI.pdf
- Description:
- IC EEPROM 4MBIT PARALLEL 32CDIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C040-20BI from Atmel is a 4-Mbit (512K × 8) paged parallel EEPROM with 200 ns read access time, JEDEC byte-wide pinout, and industrial temperature range (–40°C to +85°C). It supports automatic page write (1–256 bytes), hardware/software data protection, and DATA polling for write completion detection - used in firmware storage, configuration retention, and boot code storage in embedded controllers.
For engineers reviewing the AT28C040-20BI datasheet, AT28C040-20BI pinout, AT28C040-20BI application, or AT28C040-20BI equivalent, key selection considerations include its 200 ns read timing, 10 ms max page write cycle, 5V ±10% single-supply operation, CMOS/TTL compatibility, and industrial-grade reliability (10,000 write cycles, 10-year data retention).
Technical Context
The AT28C040-20BI implements a paged parallel EEPROM architecture with an internal 256-byte page register that latches address and data during write initiation, freeing the bus for concurrent operations. Its dual-line chip enable (CE) and output enable (OE) control enables flexible bus contention management in static RAM–compatible memory interfaces.
Write completion is verified via DATA polling on I/O7 (complement-to-data during write, true data after completion) or toggle-bit detection on I/O6. Hardware write inhibition includes VCC sense (<3.8 V), 5 ms power-on delay, and noise filtering (rejects <15 ns pulses on CE/WE).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (524,288 × 8 bits) - supports full boot image or multi-parameter configuration storage |
| Read Access Time | 200 ns - enables direct replacement of SRAM in legacy 8-bit microcontroller systems without wait-state insertion |
| Page Write Cycle Time | 10 ms maximum - allows rapid field updates of up to 256 bytes per operation, reducing system downtime |
| Endurance | 10,000 write/erase cycles - suitable for infrequent but critical configuration changes in industrial control units |
| Data Retention | 10 years at +85°C - ensures long-term validity of calibration data or security keys in unattended equipment |
| Supply Voltage | 5V ±10% - compatible with standard TTL/CMOS logic rails without external regulation |
| Operating Temperature | –40°C to +85°C - qualified for industrial environments including PLCs and motor drives |
Pinout & Package
AT28C040-20BI is packaged in a 44-pad ceramic leadless chip carrier (LCC), MIL-STD-1835 C-5 compliant, with side-braze construction and no window. Pin 1 is marked by a dot; package dimensions are 1.20" × 1.20" (30.5 mm × 30.5 mm).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A18 | Address Inputs | 19-bit address bus supporting full 512K-word addressing; A8–A18 define page boundaries for 256-byte page writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status indication |
| CE | Chip Enable | Active-low global device select; must be low with OE low and WE high for read access |
| OE | Output Enable | Active-low output control; high-Z state prevents bus contention when disabled |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; controls byte or page write initiation |
| VCC | Power Supply | +5V ±10% supply; powers core logic and memory array; VCC sense circuitry inhibits writes below ~3.8V |
| VSS | Ground | Reference return path for all signals and power; decoupling required within 10 mm of VCC pin |
| NC | No Connect | Unbonded pins (e.g., A12, A13, A15, A16, A18, etc.) - must remain floating; not tied to any internal node |
Key Features
| Feature | Design Value |
|---|---|
| Automatic Page Write | Latches up to 256 bytes internally, freeing address/data bus for other tasks while write executes autonomously |
| DATA Polling & Toggle Bit | Enables real-time, non-blocking write status monitoring using only I/O6/I/O7 - no external timers or interrupts needed |
| Hardware Write Protection | VCC sensing, 5 ms power-up delay, and 15 ns noise immunity prevent spurious writes during brown-out or EMI events |
| Software Data Protection (SDP) | User-configurable 3-byte command sequence (AAh/55h/A0h) enables/disables write lock without hardware modification |
| Device Identification Area | Dedicated 256-byte sector (7FF80H–7FFFFH) accessible via 12V on A9 - used for serialization or firmware version tagging |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up and runtime parameter updates; requires 200 ns read speed for deterministic scan-cycle timing. Use Value: 10,000-cycle endurance and 10-year data retention ensure parameter integrity across maintenance intervals without battery backup. |
Use Scenario: Holding calibrated sensor offsets and safety-critical operational limits in portable diagnostic equipment subject to frequent power cycling. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for regulatory-mandated calibration records; software data protection prevents accidental overwrites during service mode. Use Value: SDP lock and hardware VCC-sense inhibit writes during low-voltage conditions - critical for FDA-compliant data integrity. |
| Telecom Line Card Boot Firmware | Automotive Body Control Module Settings |
Use Scenario: Hosting boot loader and FPGA configuration bitstreams in carrier-grade DSLAM line cards requiring hot-swap capability. IC Role / Device Role / Timing Role: Parallel EEPROM acting as primary boot source for microcontrollers; JEDEC-compatible pinout enables drop-in replacement of legacy ROMs. Use Value: 44L LCC package provides thermal stability and vibration resistance in telecom chassis; 200 ns access avoids boot delays. |
Use Scenario: Saving user preferences (mirror position, seat memory), fault logs, and adaptive learning values in automotive BCMs operating under wide ambient temperature swings. IC Role / Device Role / Timing Role: Industrial-temperature EEPROM interfaced to 8-bit MCU via ISA-style bus; withstands –40°C cold cranking and +85°C under-hood conditions. Use Value: Extended temperature qualification and 10 ms page write allow safe reprogramming during vehicle service without engine shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M48T02-200PC1 | 2-Mbit (256K × 8), 200 ns, 5V, 32-pin PDIP; lacks page write, uses byte-write only | Lower density and slower effective update rate; no DATA polling - requires fixed tWR delay | Choose for cost-sensitive, low-update-rate applications where 2 Mbit suffices and PCB layout favors through-hole mounting |
| Microchip 25LC1024-I/P | 1-Mbit SPI EEPROM, 5 ms page write, 2.5–5.5V supply; serial interface, no parallel bus | Requires SPI controller and software driver; eliminates address/data bus routing but adds protocol overhead | Prefer for space-constrained designs where board area savings outweigh added firmware complexity and reduced throughput |
Compared with ST M48T02-200PC1 and Microchip 25LC1024-I/P, the AT28C040-20BI delivers higher density, faster parallel page writes, and hardware-assisted status detection - making it optimal for legacy 8-bit systems needing fast, deterministic, bus-compatible nonvolatile storage.
Availability
AT28C040-20BI is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostic instruments, and telecom line cards requiring stable component supply, long-lifecycle support, and guaranteed industrial-temperature performance.
Supply support for AT28C040-20BI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28C040 product line was designed for high-reliability, pin-compatible replacement of EPROM and battery-backed SRAM in industrial and telecom systems requiring field-upgradable, radiation-tolerant, and long-retention nonvolatile storage.
FAQ
What is the operating temperature range for the AT28C040-20BI?
The AT28C040-20BI is rated for industrial temperature operation from –40°C to +85°C. This specification is confirmed in the Ordering Information table (page 10) and DC/AC Operating Range table (page 4) of the official Atmel datasheet Rev. 0542B–10/98. The "I" suffix in AT28C040-20BI explicitly denotes industrial grade, distinguishing it from commercial (C) and extended (E) variants.
Does the AT28C040-20BI support page write operations, and what is the maximum page size?
Yes, the AT28C040-20BI supports automatic page write operations with a maximum page size of 256 bytes. As documented in the Features section and Device Operation chapter, the internal 256-byte page register latches address and data on write initiation, enabling simultaneous programming of up to 256 bytes within a single 10 ms internal cycle - significantly faster than sequential byte writes.
How is write completion detected on the AT28C040-20BI?
Write completion on the AT28C040-20BI is detected using either DATA polling on I/O7 (which returns complement-of-data during write and true data upon completion) or the toggle-bit method on I/O6 (which toggles between 0 and 1 until write finishes). Both methods are fully supported and characterized in the datasheet (pages 9–10), allowing host firmware to poll asynchronously without fixed timing delays.
What package type is used for the AT28C040-20BI, and how is pin 1 identified?
The AT28C040-20BI uses a 44-pad ceramic leadless chip carrier (LCC), designated as package code "44L" per Atmel's Ordering Information (page 10). Pin 1 is identified by a laser-marked dot located at the top-left corner of the package top surface, consistent with MIL-STD-1835 C-5 outline and JEDEC MO-115 standards shown in the Packaging Information section (page 11).
Is software data protection (SDP) enabled by default on the AT28C040-20BI?
No, software data protection (SDP) is disabled by default on the AT28C040-20BI. As stated in the Device Operation section (page 3), the device ships from Atmel with SDP inactive. Activation requires issuing a precise three-byte command sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h); once enabled, SDP remains active across power cycles until explicitly disabled using the corresponding unlock sequence.
AT28C040-20BI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CDIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 32-CDIP
AT28C040-20BI FAQ
1.How can I place an order for AT28C040-20BI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C040-20BI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C040-20BI reliable?
The price and inventory of AT28C040-20BI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C040-20BI is usually 5 days.
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AT28C040-20BI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C040-20BI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C040-20BI?
For technical support, including AT28C040-20BI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C040-20BI requirements.
6.How does Aetrix verify that AT28C040-20BI is sourced from the original manufacturer or authorized distributors?
All AT28C040-20BI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C040-20BI meets industry standards.
7.What is the process for return or replacement of AT28C040-20BI?
All AT28C040-20BI units undergo pre-shipment inspection (PSI). If there is an issue with AT28C040-20BI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C040-20BI part is unused and in its original packaging.
Return procedure for AT28C040-20BI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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