Microchip Technology AT28C040-20LC

Overview

AT28C040-20LC from Atmel is a 4-Mbit (512K × 8) paged parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, and hardware/software data protection. It operates on single 5V ±10% supply, supports automatic 256-byte page writes, and delivers 10,000 write cycles with 10-year data retention - used in firmware storage, configuration memory, and boot code retention for industrial controllers.

For engineers reviewing the AT28C040-20LC datasheet, AT28C040-20LC pinout, AT28C040-20LC application, or AT28C040-20LC equivalent, key selection considerations include its LCC-44 ceramic package, 200 ns read timing, page-write capability, DATA polling/Toggle Bit write completion detection, and dual hardware/software write protection mechanisms.

Technical Context

The AT28C040-20LC implements a CMOS-based paged EEPROM architecture with internal 256-byte address/data latches and an autonomous control timer for self-timed write operations. Its read interface mimics static RAM behavior with CE/OE/WE three-line control, enabling bus contention avoidance and seamless integration into legacy microcontroller systems.

Write operation modes include byte write and page write (1–256 bytes), constrained by tBLC ≤ 150 µs between successive bytes and fixed A8–A18 page addressing. End-of-write detection is supported via I/O7 DATA polling and I/O6 toggle bit, both usable at any point during the 10 ms maximum write cycle.

Key Specifications

Pinout & Package

Ceramic Leadless Chip Carrier (LCC), 44-pad, non-windowed, JEDEC MO-115 compliant, MIL-STD-1835 C-5 outline. Pin #1 identified by corner notch and metallization mark.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Compared with AT28C040-20LC, AT28C040-20JI offers wider temperature tolerance but sacrifices LCC reliability and board-space efficiency, while ST M48T02-20MH1 introduces RTC capability at the cost of EEPROM compatibility, page-write optimization, and software data protection features.

Availability

AT28C040-20LC is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, legacy embedded boot systems, and automated test instrumentation requiring stable component supply across long-lifecycle programs.

Supply support for AT28C040-20LC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for industrial, automotive, and consumer markets.

The AT28C040 belongs to Atmel's parallel EEPROM product line, designed specifically for reliable, pin-compatible replacement of EPROM and battery-backed SRAM in legacy 5V system designs requiring field-upgradable nonvolatile storage.

FAQ

What is the maximum page write size supported by the AT28C040-20LC?

The AT28C040-20LC supports up to 256 bytes per page write operation. This is enabled by its internal 256-byte address/data latch, allowing burst loading of configuration data or firmware segments without host-side timing constraints beyond the 150 µs byte-load cycle (tBLC). The AT28C040-20LC enforces page alignment: all addresses in a single page write must share identical A8–A18 values.

How does hardware write protection work on the AT28C040-20LC?

The AT28C040-20LC implements four hardware safeguards: (1) VCC sense circuitry disables writes if supply drops below ~3.8V; (2) a 5 ms internal power-on delay prevents writes until stable operation; (3) write inhibition occurs if CE is high, OE is low, or WE is high; and (4) input noise filtering rejects pulses <15 ns on CE/WE. These mechanisms ensure the AT28C040-20LC remains immune to spurious writes during power transients or EMI events.

Can the AT28C040-20LC be used as a direct replacement for standard SRAM in existing designs?

Yes - the AT28C040-20LC is accessed like static RAM during reads (CE/OE low, WE high) and maintains JEDEC-approved byte-wide pinout compatibility. However, write operations require explicit timing control and end-of-write detection (via DATA polling or Toggle Bit), unlike true SRAM. The AT28C040-20LC is ideal for read-heavy applications with infrequent writes, but not for high-frequency random writes.

What is the purpose of the 256-byte device identification area in the AT28C040-20LC?

The AT28C040-20LC reserves 256 bytes (addresses 7FF80H–7FFFFH) for user-defined device identification. Access requires raising A9 to 12V ±0.5V, after which the sector behaves identically to main memory - supporting serialization, calibration data logging, or manufacturing traceability. This dedicated area ensures critical identity information remains isolated from firmware updates and is retained across full-chip erase operations.

Does the AT28C040-20LC support chip erase, and how is it performed?

Yes - the AT28C040-20LC supports optional software chip erase using a documented 6-byte command sequence. Unlike page or byte writes, this operation erases the entire 512K-word array. Execution requires strict adherence to timing and address sequencing per Atmel's Software Chip Erase application note. The AT28C040-20LC does not support hardware (VPP-based) chip erase; all erasure is software-controlled and non-volatile.