Microchip Technology AT28C040-20LI
- Part No.:
- AT28C040-20LI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 44-CLCC
- Datasheet:
-
AT28C040-20LI.pdf
- Description:
- IC EEPROM 4MBIT PARALLEL 44CLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,895
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Product details
Overview
AT28C040-20LI from Atmel is a 4-Mbit (512K × 8) paged parallel EEPROM with 200 ns read access time, JEDEC-standard byte-wide pinout, and single 5V ±10% supply operation. It supports automatic page write of up to 256 bytes, hardware/software data protection, and Data Polling for end-of-write detection - deployed in industrial control firmware storage and embedded configuration memory.
For engineers reviewing the AT28C040-20LI datasheet, AT28C040-20LI pinout, AT28C040-20LI application, or AT28C040-20LI equivalent, key selection criteria include page write timing (≤10 ms), endurance (10,000 cycles), industrial temperature range (–40°C to +85°C), and LCC-44 package compatibility with legacy board layouts.
Technical Context
The AT28C040-20LI implements a CMOS-based parallel EEPROM architecture with internal address/data latching for 256-byte page writes and an autonomous control timer. Its dual-line chip enable (CE) and output enable (OE) logic enables bus contention avoidance in static RAM–compatible interfaces.
Write operations are validated via I/O7 Data Polling or I/O6 Toggle Bit, both functional during active programming. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs - all active without software intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 Mbit (524,288 × 8), organized as byte-addressable nonvolatile storage |
| Read Access Time | 200 ns - ensures compatibility with 5 MHz bus timing in legacy microcontroller systems |
| Page Write Cycle Time | 10 ms maximum - enables rapid field-updatable configuration blocks without system stall |
| Endurance | 10,000 write/erase cycles - supports long-term firmware revision logging in industrial equipment |
| Data Retention | 10 years at +85°C - guarantees parameter persistence across product lifecycle in unattended deployments |
| Supply Voltage | 5V ±10% - operates directly from standard TTL/CMOS logic rails without regulation overhead |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade environmental stress without derating |
Pinout & Package
AT28C040-20LI is packaged in a 44-pad ceramic leadless chip carrier (LCC), JEDEC MO-115 AA compliant, with 0.600" body width and surface-mount solder pads. Pin 1 is marked by index corner; NC pins are electrically isolated and must remain unconnected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A18 | Address Inputs | 19-bit address bus selecting one of 524,288 byte locations; A8–A18 define page boundaries for 256-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | Byte-wide parallel interface compatible with 8-bit microcontrollers; supports true read/write without external transceivers |
| CE | Chip Enable | Active-low global enable; when high, places outputs in high-impedance state and inhibits all internal operations |
| OE | Output Enable | Active-low read control; used with CE to prevent bus contention during multi-device sharing |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; rising edge initiates internal programming timer |
| VCC | Power Supply | +5V ±10% supply input; powers core logic and charge pump for EEPROM cell programming |
| VSS | Ground | Reference return path for all digital and analog circuitry; requires low-impedance PCB connection |
| NC | No Connect | Unbonded die pads; must be left floating - no routing, grounding, or voltage biasing permitted |
Key Features
| Feature | Design Value |
|---|---|
| Automatic Page Write | Latches up to 256 bytes with single WE initiation - reduces host CPU overhead and bus occupancy vs. byte-by-byte writes |
| Data Polling (I/O7) | Provides real-time write completion feedback without polling delay loops or external timers |
| Hardware Write Inhibit | VCC sense + 5 ms power-on delay prevents corruption during brown-out or cold-start conditions |
| Software Data Protection (SDP) | User-configurable 3-byte command sequence enables/disables write access - preserves factory defaults in field units |
| JEDEC Byte-Wide Pinout | Direct drop-in replacement for industry-standard EPROMs and SRAMs - eliminates PCB redesign |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing user-defined I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via parallel bus during boot and runtime reconfiguration. Use Value: 10,000-cycle endurance and 10-year data retention ensure parameter integrity over 15+ year equipment lifespans without battery backup. |
Use Scenario: Holding factory-calibrated sensor offsets, gain coefficients, and safety-critical operational limits in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, tamper-resistant calibration vault with hardware/software write lockout preventing accidental overwrite. Use Value: VCC-sense hardware protection and SDP disable command prevent corruption during battery swaps or power interruptions. |
| Telecom Line Card Boot Firmware | Avionics System Parameter Tables |
Use Scenario: Hosting boot code and FPGA configuration bitstreams in carrier-grade DSLAM line cards requiring hot-swap resilience. IC Role / Device Role / Timing Role: Parallel-boot ROM replacement with 200 ns read timing synchronized to microcontroller clock domain. Use Value: JEDEC pinout and TTL/CMOS compatibility allow reuse of existing socket footprints and address decoding logic. |
Use Scenario: Storing flight-critical lookup tables (e.g., pressure-altitude compensation, engine trim values) in certified airborne electronics. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory with extended temperature qualification (–55°C to +125°C for SL703 variant). Use Value: MIL-STD-883 tested SL703 marking confirms reliability under thermal cycling and vibration per DO-160 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-20LI | 1 Mbit (128K × 8), same LCC-44 package, 200 ns access, but lower density and no page write capability | Suitable only where firmware size ≤128 KB; lacks 256-byte burst write efficiency | Select only if board space or cost constraints preclude 4-Mbit density and page write is unnecessary |
| MX28F400BC-TI | 4-Mbit flash memory in 44-pin TSOP, 120 ns read, but requires sector erase before write and lacks byte-write capability | Requires full-sector erase (64 KB) before update - unsuitable for frequent small-parameter changes | Choose only for pure code storage where infrequent field updates justify erase latency and complexity |
Compared with AT28C256-20LI and MX28F400BC-TI, the AT28C040-20LI uniquely delivers byte- and page-level write granularity with zero-erase latency, making it optimal for dynamic configuration storage where individual parameter updates occur frequently without disrupting adjacent data.
Availability
AT28C040-20LI is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom infrastructure, and avionics requiring stable component supply with long-term obsolescence management.
Supply support for AT28C040-20LI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor designer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial and embedded markets.
The AT28C040 product line was engineered for high-reliability, pin-compatible EEPROM replacement in legacy parallel-bus systems - emphasizing zero-erase write flexibility, industrial temperature resilience, and hardware/software dual-protection.
FAQ
What is the operating temperature range for the AT28C040-20LI?
The AT28C040-20LI is rated for industrial operation from –40°C to +85°C. This range is confirmed in the DC and AC Operating Range table and applies to both read and write functions. The SL703 variant extends the temperature qualification to –55°C to +125°C for the case, though write operation remains limited to –40°C to +85°C per specification.
Does the AT28C040-20LI require external high-voltage programming signals?
No. The AT28C040-20LI uses on-chip charge pump circuitry to generate internal programming voltages. It operates from a single 5V ±10% supply - no external VPP or 12V signals are needed. All write operations, including page writes and software chip erase, are executed using standard logic-level CE, WE, and OE controls.
How does Data Polling work on the AT28C040-20LI?
Data Polling on the AT28C040-20LI uses I/O7: during a write cycle, reading the last written byte returns the complement of the data until programming completes, then returns true data. This allows the host to poll I/O7 without timing loops or external delays - the transition indicates write completion and readiness for the next access.
Can the AT28C040-20LI be used as a direct replacement for standard EPROMs like the 27C512?
The AT28C040-20LI shares JEDEC byte-wide pinout compatibility with many EPROMs, but it is not a direct drop-in replacement for 27C512 due to differing pin functions: 27C512 uses OE/PGM, while AT28C040-20LI uses WE for write control and has no PGM pin. Address bus width also differs (A0–A15 vs. A0–A18). Board-level validation is required.
What is the purpose of the extra 256 bytes of EEPROM in the AT28C040-20LI?
The AT28C040-20LI includes 256 bytes of dedicated identification EEPROM at addresses 7FF80H–7FFFFH. Accessed by raising A9 to 12V ±0.5V, this area stores device-specific data such as serial numbers, calibration IDs, or manufacturing traceability codes - separate from main array and immune to standard write commands.
AT28C040-20LI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 44-CLCC
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-CLCC (16.55x16.55)
AT28C040-20LI FAQ
1.How can I place an order for AT28C040-20LI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C040-20LI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C040-20LI reliable?
The price and inventory of AT28C040-20LI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C040-20LI is usually 5 days.
3.What payment methods are accepted for AT28C040-20LI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C040-20LI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C040-20LI?
AT28C040-20LI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C040-20LI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C040-20LI?
For technical support, including AT28C040-20LI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C040-20LI requirements.
6.How does Aetrix verify that AT28C040-20LI is sourced from the original manufacturer or authorized distributors?
All AT28C040-20LI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C040-20LI meets industry standards.
7.What is the process for return or replacement of AT28C040-20LI?
All AT28C040-20LI units undergo pre-shipment inspection (PSI). If there is an issue with AT28C040-20LI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C040-20LI part is unused and in its original packaging.
Return procedure for AT28C040-20LI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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