Microchip Technology AT28C040-25FC

Overview

AT28C040-25FC from Atmel is a 4-Mbit (512K × 8) paged parallel EEPROM with JEDEC-standard byte-wide pinout, 250 ns read access time, and hardware/software data protection. It operates on single 5V ±10% supply, supports automatic 256-byte page writes, and is used in firmware storage, configuration memory, and boot code retention for industrial controllers and embedded systems.

For engineers reviewing the AT28C040-25FC datasheet, AT28C040-25FC pinout, AT28C040-25FC application, or AT28C040-25FC equivalent, key selection criteria include page write timing (≤10 ms), DATA polling/Toggle Bit write completion detection, 10,000-cycle endurance, 10-year data retention, and LCC-44 ceramic package compatibility with high-reliability board-level mounting.

Technical Context

The AT28C040-25FC implements a CMOS-based paged EEPROM architecture with internal address/data latching for up to 256 bytes per write cycle and an autonomous control timer. Its dual-line chip enable (CE) and output enable (OE) logic enables bus contention avoidance in shared-memory systems.

It features VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, noise filtering on WE/CE inputs (<15 ns rejection), and optional software data protection (SDP) activated via three-byte command sequence at addresses 5555H/2AAAH/5555H. Device identification space (256 bytes at 7FF80H–7FFFFH) requires A9 = 12 V ±0.5 V.

Key Specifications

Pinout & Package

Ceramic Leadless Chip Carrier (LCC), 44-pad, non-windowed, JEDEC MO-115 / MIL-STD-1835 C-5 compliant. Pin 1 marked by corner cut; solderable side-braze terminations for hermetic reliability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar paged parallel EEPROM applications.

Compared with AT28C040-25FC, AT28C040-25JI offers identical functionality with extended temperature support, while ST M48T02-100PC1 serves distinct low-density, RTC-coupled use cases - neither is pin-compatible, but the Atmel variant maintains full backward compatibility within its speed/package family.

Availability

AT28C040-25FC is available at Aetrix Electronics and suitable for industrial PLCs, legacy BIOS platforms, medical calibration systems, and telecom line cards requiring stable component supply, long-term obsolescence management, and verified ceramic-LCC reliability.

Supply support for AT28C040-25FC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in nonvolatile memory, microcontrollers, and secure authentication ICs for industrial and embedded markets.

The AT28C040 product line was designed for high-reliability, pin-compatible replacement of UV-erasable EPROMs in legacy 5 V systems, emphasizing endurance, data retention, and robust write-protection schemes.

FAQ

What is the maximum page write time specification for AT28C040-25FC?

The AT28C040-25FC has a maximum page write cycle time of 10 ms, as specified in the AC Write Characteristics table. This applies to all 1–256 byte writes within a single page (defined by A8–A18). The internal control timer ensures consistent timing regardless of host bus speed, and write completion can be confirmed via DATA polling on I/O7 or Toggle Bit behavior on I/O6. This value is guaranteed across the commercial temperature range (0°C to +70°C).

Does AT28C040-25FC support both CE-controlled and WE-controlled write operations?

Yes, AT28C040-25FC supports both CE-controlled and WE-controlled write operations, as defined in the Device Operation section. A low pulse on either CE (with WE high and OE high) or WE (with CE low and OE high) initiates a byte or page write. The address is latched on the falling edge of whichever signal occurs last, and data is latched on the first rising edge. Both methods are fully supported and electrically identical in timing and outcome for the AT28C040-25FC.

How is software data protection (SDP) enabled and disabled on AT28C040-25FC?

Software data protection (SDP) on AT28C040-25FC is enabled by writing three specific bytes (0xAA, 0x55, 0xA0) to addresses 0x5555, 0x2AAA, and 0x5555 respectively. Disabling SDP requires a different 3-byte sequence: 0xAA, 0x55, 0x80 to the same addresses. Once enabled, SDP remains active across power cycles until explicitly disabled. The AT28C040-25FC ships with SDP disabled, and all command sequences must comply with page write timing constraints.

What package type does AT28C040-25FC use, and is it RoHS-compliant?

AT28C040-25FC uses a 44-pad Ceramic Leadless Chip Carrier (LCC), designated as package code "44L" per Atmel's ordering information. It conforms to JEDEC MO-115 and MIL-STD-1835 C-5 outlines. While the original datasheet predates RoHS enforcement, this LCC variant is lead-based (SnPb finish); RoHS-compliant versions were not offered for this speed/package combination. For RoHS requirements, consult Microchip's current cross-reference or consider migration paths.

Can AT28C040-25FC be used as a direct replacement for standard 27C040 EPROMs?

AT28C040-25FC provides JEDEC-approved byte-wide pinout compatibility with 27C040 EPROMs and shares identical address/data/control pin assignments (A0–A18, I/O0–I/O7, CE, OE, WE). However, it requires no UV erasure and supports in-system reprogramming. As a functional replacement, it eliminates EPROM programmers and UV erasers but mandates verification of write-enable logic and power sequencing - the AT28C040-25FC is not a blind socket replacement due to active write control differences.