Microchip Technology AT28C17E-15SC

Overview

AT28C17E-15SC from Atmel is a 16K-bit (2,048 × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, 200 µs fast byte write, and CMOS/TTL-compatible I/O. It operates at 5V ±10%, supports commercial temperature range (0°C to 70°C), and delivers 100 µA standby current-ideal for firmware storage in embedded controllers requiring nonvolatile, microprocessor-direct memory access.

For engineers reviewing the AT28C17E-15SC datasheet, AT28C17E-15SC pinout, AT28C17E-15SC application, or AT28C17E-15SC equivalent, key selection criteria include self-timed write cycle, RDY/BUSY open-drain signaling, DATA POLLING support, and high endurance (10⁵ cycles) in SOIC-28 packaging.

Technical Context

The AT28C17E-15SC implements a fully self-timed byte write architecture with internal address/data latches and an automatic clear-before-write sequence. Its dual write detection methods-RDY/BUSY open-drain output and I/O7 data polling-enable deterministic timing control without external wait-state logic.

It functions as a drop-in SRAM replacement for reads and writes, requiring no external timing components. The device enforces write protection via VCC sense (<3.8V inhibition), 5 ms power-on delay, and active-level CE/OE/WE gating-ensuring robust immunity to spurious writes during power transitions.

Key Specifications

Pinout & Package

AT28C17E-15SC is supplied in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package per JEDEC MS-011 AB, with pin 1 marked by a beveled corner and standard lead pitch of 0.050".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C256-15SC, the AT28C17E-15SC offers identical timing and package but half the density-ideal where board space and cost constrain expansion. Versus ST M28W160ECB90ZC1, it provides true byte-erasable operation in smaller SOIC-28 footprint, avoiding flash erase complexity and larger package.

Availability

AT28C17E-15SC is available at Aetrix Electronics and suitable for industrial PLCs, medical instrumentation, automotive body control modules, and point-of-sale terminals requiring stable component supply, long-lifecycle support, and guaranteed 5V parallel EEPROM compatibility.

Supply support for AT28C17E-15SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for embedded systems.

The AT28C17E-15SC belongs to Atmel's parallel EEPROM product line, designed specifically for microprocessor-direct, byte-addressable nonvolatile storage in industrial, medical, and automotive control applications where SRAM-like interface simplicity and high endurance are essential.

FAQ

What is the maximum write cycle time for AT28C17E-15SC?

The AT28C17E-15SC has a maximum byte write cycle time of 200 µs, as confirmed in the AC Write Characteristics table. This is the "E" variant's defining specification-distinct from the standard AT28C17-15SC, which requires up to 1 ms per byte. The 200 µs value applies under standard 5V operation and commercial temperature range, enabling rapid field updates without system stall.

Does AT28C17E-15SC support hardware write protection?

Yes, AT28C17E-15SC implements three hardware write protection mechanisms: (1) VCC sense that disables writing below ~3.8V, (2) automatic 5 ms power-on delay before write enable, and (3) active-level gating-write is inhibited unless CE is low, OE is high, and WE is low. These features operate independently of software and ensure immunity to noise-induced or brown-out writes.

Can AT28C17E-15SC be used as a direct replacement for standard SRAM in existing designs?

AT28C17E-15SC supports SRAM-like read access with identical timing (150 ns), but write behavior differs: it requires explicit WE strobing and write completion detection (via RDY/BUSY or DATA POLLING). While pinout and read interface match, existing SRAM write routines must be modified to accommodate self-timed writes and status polling-making it a functional, not drop-in, replacement.

What is the purpose of the RDY/BUSY pin on AT28C17E-15SC?

The RDY/BUSY pin (Pin 1) on AT28C17E-15SC is an open-drain output that actively pulls low during byte write execution and releases to high-impedance upon completion. It enables hardware-driven write synchronization-multiple devices can share one RDY/BUSY line with a single pull-up resistor, simplifying timing-critical systems where software polling is undesirable or unavailable.

How does DATA POLLING work on AT28C17E-15SC?

During a byte write, AT28C17E-15SC returns the complement of the written data on I/O7 while other outputs remain indeterminate; once the write completes, true data appears on all I/O lines. This allows the host microcontroller to poll I/O7-reading until the bit toggles from complement to true-to detect write completion without external hardware or fixed delays.