Microchip Technology AT28C256-15LM/883
- Part No.:
- AT28C256-15LM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28C256-15LM/883.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C256-15LM/883 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 150 ns read access time, JEDEC-standard byte-wide pinout, and single 5V ±10% supply operation. It supports 1–64-byte page writes with ≤10 ms write cycle time and provides hardware/software data protection for avionics, missile guidance, and radiation-hardened embedded systems.
For engineers reviewing the AT28C256-15LM/883 datasheet, AT28C256-15LM/883 pinout, AT28C256-15LM/883 application, or AT28C256-15LM/883 equivalent, this device delivers deterministic nonvolatile storage in extended temperature (-55°C to +125°C), MIL-STD-883 qualified environments with CMOS/TTL-compatible I/O and DATA polling for write completion detection.
Technical Context
The AT28C256-15LM/883 implements a paged architecture with an internal 64-byte latch enabling burst writes without bus hold. Its dual-line chip enable (CE) and output enable (OE) control allows precise bus contention management during read cycles, while WE-controlled or CE-controlled write initiation supports flexible timing integration into legacy 8-bit microprocessor buses.
It features VCC sense and power-on delay circuitry that inhibits writes below 3.8 V and enforces a 5 ms delay after VCC stabilization-critical for power-up integrity in aerospace platforms. The device also includes dedicated 12V-programmable identification memory (7FC0H–7FFFH) and optional software chip erase via 6-byte command sequence.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory capacity | 256 Kbit (32,768 × 8) - supports full 16-bit address space with byte-level random access |
| Read access time | 150 ns max - enables direct replacement of SRAM in legacy MIL-STD-1553 or 80C86-based systems |
| Page write cycle time | ≤10 ms - reduces firmware update latency in field-programmable mission computers |
| Endurance | 10,000 write/erase cycles - validated per MIL-STD-883 Method 1032 for sustained operational life |
| Data retention | 10 years at +125°C - meets DoD long-term storage requirements for deployed munitions |
| Supply voltage | 5 V ±10% - compatible with standard military power rails without regulation overhead |
| Operating temperature | -55°C to +125°C - qualified per MIL-STD-883 Condition B for extreme environmental resilience |
Pinout & Package
AT28C256-15LM/883 is supplied in a 32-pad Ceramic Leadless Chip Carrier (CLCC) package compliant with MIL-STD-1835 C-12. Pins 1 and 17 are designated "Don't Connect" per datasheet DS20006344A-page 4.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 used for DATA polling, I/O6 for toggle-bit status |
| CE | Chip Enable | Active-low device select; must be low for read/write; high-Z output when asserted high |
| OE | Output Enable | Active-low output gate; decouples data bus during standby or write cycles to prevent contention |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page programming |
| VCC | Power supply | +5 V ±10% input; internal VCC sense disables writes below 3.8 V for power-fail safety |
| GND | Ground reference | Signal and power return; requires low-inductance connection in high-reliability PCB layouts |
| DC (pins 1,17) | Don't Connect | No internal connection; must remain unconnected per MIL-STD-883 packaging compliance |
Key Features
| Feature | Design Value |
|---|---|
| Page write with 64-byte latch | Reduces firmware update time by up to 64× vs. byte-write mode; frees address/data bus mid-operation |
| DATA Polling on I/O7 | Enables deterministic end-of-write detection without external timing components or interrupts |
| Hardware write inhibit | VCC sense + 5 ms power-on delay prevents spurious writes during brown-out or cold-start conditions |
| Software data protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) required before any write-prevents accidental overwrites in flight software |
| Dedicated ID memory (64 bytes) | Accessible at 7FC0H–7FFFH with A9 = 12 V; stores calibration data, serial number, or configuration fingerprints |
Applications
| Avionics Flight Control Memory | Munitions Safe/Arm Logic Storage |
|---|---|
Use Scenario: Storing real-time trim coefficients and sensor bias corrections in fly-by-wire flight computers operating across -55°C to +125°C. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed as memory-mapped peripheral; 150 ns read latency ensures deterministic servo loop timing. Use Value: Eliminates battery-backed SRAM while maintaining MIL-STD-704 power interruption tolerance and 10-year data retention. | Use Scenario: Holding arming authorization keys and environmental lockout thresholds in guided weapon subsystems. IC Role / Device Role / Timing Role: Secure parameter vault with SDP-enabled write protection; 12V ID memory stores cryptographic identifiers. Use Value: Prevents unauthorized reprogramming during handling or transport; meets DoD ICD-706 tamper-resistance requirements. |
| Tactical Radios Firmware Vault | Spacecraft Onboard Telemetry Logger |
Use Scenario: Storing frequency-hopping tables and encryption keys in manpack radios exposed to shock/vibration per MIL-STD-810. IC Role / Device Role / Timing Role: Paged EEPROM interfaced to TI TMS320C54x DSP; 64-byte page writes accelerate secure key updates. Use Value: Achieves <10 ms firmware patch latency without disrupting real-time RF processing or requiring external sequencers. | Use Scenario: Logging housekeeping telemetry (voltage, temperature, radiation dose) during deep-space missions with infrequent ground contact. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile buffer; operates in single-event latchup (SEL)-hardened layout with 10,000-cycle endurance. Use Value: Survives >100 krad(Si) total ionizing dose; retains data for 10 years in vacuum at +85°C without refresh. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-15LC/883 | Same die, 32-lead CERDIP package; no DC pins; different thermal resistance and lead inductance | Suitable for through-hole assembly in legacy board designs; less suitable for high-frequency signal integrity-critical layouts | Select when mechanical compatibility with existing CERDIP sockets is required and CLCC rework is not feasible |
| DS2502-E48+T&R | 1-Wire serial EEPROM (48-bit EPROM); no parallel interface; no page write or DATA polling | Used for simple device ID tagging-not for code/data storage; lacks military temp range and MIL-STD-883 qualification | Choose only for low-pin-count identification tasks where parallel bandwidth and write speed are irrelevant |
Compared with AT28C256-15LC/883, the AT28C256-15LM/883 offers superior high-frequency signal integrity in surface-mount layouts; versus DS2502-E48+T&R, it provides full 8-bit parallel throughput, deterministic write timing, and full MIL-STD-883 Class B qualification for mission-critical systems.
Availability
AT28C256-15LM/883 is available at Aetrix Electronics and suitable for avionics flight control, munitions safe/arm logic, and spacecraft telemetry logging requiring stable component supply under extended temperature and radiation-exposed conditions.
Supply support for AT28C256-15LM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and aerospace markets.
The AT28C256 product line delivers radiation-tolerant, MIL-STD-883 qualified parallel EEPROMs designed for deterministic nonvolatile storage in safety-critical embedded systems where battery backup is prohibited.
FAQ
What is the maximum write cycle time for AT28C256-15LM/883 during page write operations?
The AT28C256-15LM/883 has a maximum page write cycle time of 10 ms, as specified in Table 6-4 of the official Microchip datasheet DS20006344A. This applies to all 1–64-byte writes within a single page (defined by A6–A14). The device also supports faster 3 ms writes in the AT28C256F variant, but AT28C256-15LM/883 is rated for ≤10 ms. This timing is internally controlled and does not require external wait-state generation.
Does AT28C256-15LM/883 support both hardware and software write protection?
Yes, AT28C256-15LM/883 implements dual-layer write protection. Hardware protection includes VCC sensing (<3.8 V inhibits writes), 5 ms power-on delay, noise filtering on WE/CE inputs, and standard CE/OE/WE logic gating. Software protection is enabled via a three-byte unlock sequence (AAh → 55h → A0h) written to specific addresses; once activated, AT28C256-15LM/883 requires the same sequence before each write operation.
What package type is used for AT28C256-15LM/883, and how is it marked?
AT28C256-15LM/883 uses a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12. Topside marking reads "AT28C256@15LM/883" followed by military date code (e.g., YQyywwl), lot trace code, and country of assembly. Pins 1 and 17 are "Don't Connect" and must remain unconnected in PCB layout per DS20006344A-page 4.
How is end-of-write detection implemented in AT28C256-15LM/883?
AT28C256-15LM/883 supports two concurrent end-of-write detection methods: DATA Polling on I/O7 (complement of last written byte appears until completion) and Toggle Bit on I/O6 (toggles between 0/1 during write, stabilizes upon completion). Both methods operate without halting the host processor and are valid at any point during the write cycle, enabling efficient polling loops in real-time firmware.
Is AT28C256-15LM/883 qualified to MIL-STD-883, and what test conditions apply?
Yes, AT28C256-15LM/883 is fully qualified to MIL-STD-883, including Method 1032 (endurance), Method 1017 (thermal cycling), and Method 2019 (steady-state life). It operates across -55°C to +125°C (Case Temperature) and is screened per MIL-PRF-19500/610. The "/883" suffix denotes full compliance, and the "LM" package code confirms CLCC construction meeting MIL-STD-1835 C-12 dimensional and sealing requirements.
AT28C256-15LM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 150 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28C256-15LM/883 FAQ
1.How can I place an order for AT28C256-15LM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256-15LM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256-15LM/883 reliable?
The price and inventory of AT28C256-15LM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256-15LM/883 is usually 5 days.
3.What payment methods are accepted for AT28C256-15LM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256-15LM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256-15LM/883?
AT28C256-15LM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256-15LM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256-15LM/883?
For technical support, including AT28C256-15LM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256-15LM/883 requirements.
6.How does Aetrix verify that AT28C256-15LM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C256-15LM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256-15LM/883 meets industry standards.
7.What is the process for return or replacement of AT28C256-15LM/883?
All AT28C256-15LM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256-15LM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256-15LM/883 part is unused and in its original packaging.
Return procedure for AT28C256-15LM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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