Microchip Technology AT28C256-20FM/883-815
- Part No.:
- AT28C256-20FM/883-815
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CFlatPack
- Datasheet:
-
AT28C256-20FM/883-815.pdf
- Description:
- IC EEPROM 256KBIT PAR 28FLATPK
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C256-20FM/883-815 from Microchip Technology is a military-grade 256-Kbit paged parallel EEPROM organized as 32,768 × 8, featuring 200 ns read access time, 10 ms maximum page write cycle time, and single 5V ±10% supply operation. It supports hardware/software data protection, DATA polling, and toggle-bit write completion detection for embedded avionics and defense systems requiring nonvolatile storage with high reliability under extreme temperature.
For engineers reviewing the AT28C256-20FM/883-815 datasheet, AT28C256-20FM/883-815 pinout, AT28C256-20FM/883-815 application, or AT28C256-20FM/883-815 equivalent, this page delivers verified military-spec electrical parameters, JEDEC-compliant byte-wide pin mapping, endurance (10,000 cycles) and retention (10 years) specifications, and real-world use cases in radiation-tolerant control modules and secure boot memory.
Technical Context
The AT28C256-20FM/883-815 implements a paged architecture with a 64-byte internal latching register, enabling simultaneous writes of 1–64 bytes within a single page defined by address bits A6–A14. Its dual-line chip enable (CE) and output enable (OE) control allows flexible bus contention management during read operations.
Write completion is confirmed via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle-bit detection, both operable at any point during the internal programming period. Hardware write inhibition includes VCC sense (<3.8 V), 5 ms power-on delay, and noise filtering on WE/CE inputs (15 ns pulse rejection).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8) - provides sufficient nonvolatile storage for firmware images or configuration tables in MIL-STD-883 Class B systems. |
| Read Access Time | 200 ns max - meets timing requirements for direct interface with legacy 8-bit microcontrollers operating at ≤5 MHz. |
| Page Write Cycle Time | 10 ms max - enables efficient bulk updates without external timing circuitry; compatible with MIL-STD-883 test conditions. |
| Endurance | 10,000 write/erase cycles - validated per MIL-STD-883 Method 1033 for mission-critical reprogramming scenarios. |
| Data Retention | 10 years at -55°C to +125°C - guaranteed under full military temperature range without refresh. |
| Supply Voltage | 5V ±10% - operates from standard logic rail; no auxiliary voltage required for programming or erase. |
| Standby Current | 300 µA CMOS - minimizes quiescent power in always-on avionics subsystems. |
Pinout & Package
AT28C256-20FM/883-815 is supplied in a 32-lead flatpack (MIL-STD-1835 F-12 Config B), hermetically sealed ceramic package rated for -55°C to +125°C operation. Pin 1 is marked with a notch or dot; pins 1–28 follow JEDEC byte-wide layout with A0–A14 address inputs, I/O0–I/O7 bidirectional data lines, and CE/OE/WE control signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus selecting one of 32,768 memory locations; A6–A14 define 64-byte page boundaries for write operations. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; I/O7 used for DATA polling (complement output during write), I/O6 for toggle-bit status indication. |
| CE | Chip Enable | Active-low device select; must be low with OE low and WE high for read access; initiates write when pulsed low with OE high. |
| OE | Output Enable | Active-low output gate; controls data bus drive; high-Z state prevents bus contention when disabled. |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; combined with CE and OE determines operating mode per Table 6-1. |
| VCC, GND | Power Supply | Single 5V ±10% supply with CMOS-compatible standby current (≤300 µA); no separate VPP required for programming. |
Key Features
| Feature | Design Value |
|---|---|
| Paged Write Architecture | 64-byte internal latch enables burst writes without CPU bus hold; reduces system overhead vs. byte-by-byte programming. |
| Hardware Write Protection | VCC sense + 5 ms power-on delay + noise filtering ensures immunity to brown-out and EMI-induced spurious writes. |
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) enables selective write-enable; persists across power cycles and protects entire array. |
| Write Completion Detection | Dual-mode confirmation: I/O7 DATA polling (complement-to-data) or I/O6 toggle-bit eliminates need for fixed delays or external timers. |
| MIL-STD-883 Qualified | Screened to Class B requirements including temperature cycling, hermeticity, and radiation hardness assurance per 5962-88525 spec. |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
Use Scenario: Storing calibrated sensor coefficients and flight envelope limits in fly-by-wire ECUs operating at -55°C to +125°C. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to 80C32 microcontroller via parallel bus; accessed during power-up initialization and runtime calibration updates. Use Value: 200 ns read access ensures deterministic boot timing; 10,000-cycle endurance supports field recalibration without replacement. |
Use Scenario: Holding frequency-hopping tables and encryption keys in manpack radios subjected to shock/vibration and thermal cycling. IC Role / Device Role / Timing Role: Secure parameter store with software data protection enabled; write-protected except during authorized key loading sequences. Use Value: SDP prevents accidental overwrites during RF transmission transients; 10-year data retention eliminates periodic refresh maintenance. |
| Military Vehicle Engine Control | Secure Boot ROM Extension |
Use Scenario: Storing emission control maps and diagnostic fault logs in diesel engine controllers deployed in desert environments. IC Role / Device Role / Timing Role: Field-upgradable firmware parameter bank; updated via CAN gateway using page-write bursts to minimize bus occupancy. Use Value: 10 ms page write time enables rapid map updates; 300 µA standby current extends battery life during vehicle dormancy. |
Use Scenario: Extending boot ROM in secure processors to store cryptographic root-of-trust certificates and anti-rollback counters. IC Role / Device Role / Timing Role: Tamper-resistant persistent store; accessed only by trusted execution environment during secure boot chain verification. Use Value: Hermetic 32-lead flatpack resists moisture ingress; hardware write inhibit blocks unauthorized writes during voltage glitches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-20JM/883 | Same die, 32-lead CERDIP package instead of flatpack; identical AC/DC specs and MIL-STD-883 screening. | Preferred where board-level hermetic sealing or leaded solder joint reliability is prioritized over footprint size. | Select AT28C256-20JM/883 if CERDIP mechanical robustness is required; otherwise AT28C256-20FM/883-815 offers lower profile and proven flatpack thermal performance. |
| DS2502-E48+T&R | 1-Wire serial EEPROM (4Kbit), not parallel; no page write, no DATA polling; 100K endurance but 5V-only operation. | Suitable only for low-pin-count, low-bandwidth applications where serial interface suffices and parallel bus is unavailable. | Choose DS2502-E48+T&R only when pin count constraints prohibit parallel interfaces; it cannot replace AT28C256-20FM/883-815 in timing-critical or high-throughput use cases. |
Compared with AT28C256-20JM/883, the AT28C256-20FM/883-815 offers identical functionality in a space-saving flatpack, while DS2502-E48+T&R trades parallel speed and page-write efficiency for serial simplicity-making it unsuitable for direct substitution in existing AT28C256-based designs.
Availability
AT28C256-20FM/883-815 is available at Aetrix Electronics and suitable for avionics flight control, tactical radio configuration, military vehicle engine control, and secure boot ROM extension requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT28C256-20FM/883-815 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with deep expertise in military-qualified components and long-term product lifecycle support.
The AT28C256 product line was designed specifically for high-reliability embedded systems requiring radiation-tolerant, temperature-hardened nonvolatile memory with deterministic timing and robust data integrity features.
FAQ
What is the maximum operating temperature range for the AT28C256-20FM/883-815?
The AT28C256-20FM/883-815 is qualified for operation from -55°C to +125°C per MIL-STD-883 Method 1010. This full military temperature range is validated across all DC and AC parameters, including 200 ns read access time and 10 ms page write cycle, ensuring reliable function in harsh environmental deployments where commercial-grade EEPROMs would fail.
Does the AT28C256-20FM/883-815 require an external high-voltage supply for programming?
No, the AT28C256-20FM/883-815 operates from a single 5V ±10% supply for both read and write functions. Unlike older EPROMs, it does not require VPP = 12.5V or other elevated programming voltages. The internal charge pump generates necessary voltages, and the 12V requirement mentioned in the datasheet applies only to optional chip erase mode-not standard page or byte writes.
How is write completion detected on the AT28C256-20FM/883-815?
Write completion on the AT28C256-20FM/883-815 is confirmed using either DATA polling on I/O7 (which outputs the complement of written data until completion) or the toggle-bit method on I/O6 (which toggles between 0 and 1 during programming). Both methods are functional at any time during the write cycle and eliminate reliance on fixed timing delays.
Is software data protection (SDP) enabled by default on the AT28C256-20FM/883-815?
No, the AT28C256-20FM/883-815 ships with software data protection disabled. SDP must be explicitly enabled using the three-byte unlock sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h). Once enabled, SDP remains active across power cycles and requires the disable sequence to deactivate-ensuring persistent protection against inadvertent writes.
What package type is used for the AT28C256-20FM/883-815?
The AT28C256-20FM/883-815 uses a 32-lead flatpack (MIL-STD-1835 F-12 Config B), a ceramic bottom-brazed hermetic package with 0.600" body width. It features a JEDEC-compliant byte-wide pinout and is screened to Class B requirements, including thermal cycling, fine leak testing, and radiation hardness assurance per specification 5962-88525.
AT28C256-20FM/883-815 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-FlatPack, Ceramic Bottom-Brazed
AT28C256-20FM/883-815 FAQ
1.How can I place an order for AT28C256-20FM/883-815 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256-20FM/883-815 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256-20FM/883-815 reliable?
The price and inventory of AT28C256-20FM/883-815 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256-20FM/883-815 is usually 5 days.
3.What payment methods are accepted for AT28C256-20FM/883-815?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256-20FM/883-815 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256-20FM/883-815?
AT28C256-20FM/883-815 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256-20FM/883-815 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256-20FM/883-815?
For technical support, including AT28C256-20FM/883-815 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256-20FM/883-815 requirements.
6.How does Aetrix verify that AT28C256-20FM/883-815 is sourced from the original manufacturer or authorized distributors?
All AT28C256-20FM/883-815 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256-20FM/883-815 meets industry standards.
7.What is the process for return or replacement of AT28C256-20FM/883-815?
All AT28C256-20FM/883-815 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256-20FM/883-815, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256-20FM/883-815 part is unused and in its original packaging.
Return procedure for AT28C256-20FM/883-815:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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