Microchip Technology AT28C256-20LM/883
- Part No.:
- AT28C256-20LM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28C256-20LM/883.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:

- Shipping:

Inventory:3,535
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Product details
Overview
AT28C256-20LM/883 from Microchip Technology is a military-grade paged parallel EEPROM with 256-Kbit (32,768 × 8) organization, 200 ns read access time, single 5V ±10% supply, and JEDEC-approved byte-wide pinout. It supports 1–64-byte page writes with ≤10 ms write cycle time and operates across –55°C to +125°C for avionics and defense subsystems requiring nonvolatile configuration storage.
For engineers reviewing the AT28C256-20LM/883 datasheet, AT28C256-20LM/883 pinout, AT28C256-20LM/883 application, or AT28C256-20LM/883 equivalent, this page delivers verified military-spec electrical characteristics, page-write timing constraints, hardware/software data protection implementation, and CLCC package terminal mapping per DS20006344A.
Technical Context
The AT28C256-20LM/883 implements a CMOS-based paged architecture with internal 64-byte latches and autonomous control timer, enabling simultaneous multi-byte writes without external address/data bus hold. Its dual-line chip enable (CE) and output enable (OE) logic ensures deterministic bus contention avoidance in MIL-STD-1553 or discrete control backplanes.
It integrates VCC-sense circuitry (write inhibit below 3.8 V), 5 ms power-on delay, noise filtering (<15 ns pulse rejection on WE/CE), and optional software data protection (SDP) via three-byte unlock sequence. Device identification space (64 bytes at 7FC0H–7FFFH) requires A9 = 12 V ±0.5 V for access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 256 Kbit (32,768 × 8) - supports full 16-bit address space with byte-level random access |
| Read Access Time | 200 ns max - meets timing budgets for 5 MHz synchronous bus interfaces in legacy military controllers |
| Page Write Cycle | ≤10 ms - enables firmware patching or calibration table updates without system reset |
| Operating Temperature | –55°C to +125°C - qualified per MIL-PRF-38535 Class B for extended environmental survivability |
| Supply Voltage | 5 V ±10% - compatible with standard TTL/CMOS logic rails without regulation overhead |
| Endurance | 10,000 write cycles - sufficient for infrequent field-upgrade scenarios in sealed avionics enclosures |
| Data Retention | 10 years - validated under accelerated life testing at 125°C for long-term mission-critical logging |
| Standby Current | 300 µA CMOS - enables low-power sleep modes in battery-backed telemetry recorders |
Pinout & Package
AT28C256-20LM/883 is supplied in a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12, with pins 1 and 17 designated "Don't Connect" per datasheet DS20006344A-page 4. The package provides hermetic sealing and thermal stability for high-reliability aerospace deployments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 used for DATA Polling, I/O6 for Toggle Bit status indication |
| CE | Chip Enable | Active-low selection signal; must be stable before address setup to avoid spurious writes |
| OE | Output Enable | Active-low read control; high-Z state prevents bus contention during CE-only asserts |
| WE | Write Enable | Active-low write strobe; combined with CE/OE logic to initiate byte or page programming |
| VCC | Power Supply | +5 V ±10% main supply; internal VCC-sense disables writes below 3.8 V typical |
| GND | Ground Reference | Signal and power return; decoupling required within 10 mm of VCC pin per MIL-HDBK-454 |
| DC (pins 1, 17) | No Connect | Unused terminals; must remain unconnected per manufacturer marking specification |
Key Features
| Feature | Design Value |
|---|---|
| Automatic Page Write | Internal 64-byte latch frees address/data bus after initial byte load, enabling concurrent host CPU operations |
| DATA Polling | I/O7 returns complement of last written byte until write completes - eliminates need for fixed timeout delays |
| Hardware Write Protection | VCC-sense + 5 ms power-on delay + noise filtering prevent corruption during brown-out or EMI transients |
| Software Data Protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) enables selective write-enable per memory region |
| Device Identification Area | 64-byte reserved zone (7FC0H–7FFFH) accessible at 12 V on A9 - supports traceability and firmware version tagging |
Applications
| Avionics Configuration Storage | MIL-STD-1553 Bus Controller Firmware |
|---|---|
Use Scenario: Storing flight control parameter sets, sensor calibration coefficients, and mission-specific configuration profiles in airborne vehicle management computers. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via parallel address/data bus during boot initialization and runtime reconfiguration. Use Value: 10-year data retention and –55°C to +125°C operation ensure integrity across extended storage and extreme thermal cycling in unpressurized bays. | Use Scenario: Holding protocol stack microcode and message descriptor tables for dual-redundant MIL-STD-1553 bus controllers in tactical aircraft. IC Role / Device Role / Timing Role: Parallel EEPROM mapped into controller's memory space for fast read access during BC message scheduling and status reporting. Use Value: 200 ns read access meets tight timing margins for 1 Mbps bus arbitration cycles without wait-state insertion. |
| Tactical Radio Frequency Synthesizer Calibration | Secure Crypto Module Key Storage |
Use Scenario: Storing temperature-compensated DAC lookup tables and VCO tuning offsets in SDR transceivers deployed in ground-mobile radios. IC Role / Device Role / Timing Role: Calibration data repository updated during factory alignment and field recalibration using page-write mode. Use Value: ≤10 ms page write time allows real-time correction uploads during maintenance windows without radio downtime. | Use Scenario: Securing cryptographic key material and device identity certificates in NSA-certified Type 1 encryption modules. IC Role / Device Role / Timing Role: Tamper-resistant nonvolatile storage with hardware/software write protection preventing unauthorized key overwrites. Use Value: SDP lock sequence and VCC-sense inhibit ensure keys remain intact during power faults or voltage glitch attacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-20JC | Commercial-grade CERDIP package; rated –40°C to +85°C; no MIL-PRF-38535 qualification | Lacks radiation tolerance and extended temperature range; unsuitable for flight-critical systems | Select only for ground-test fixtures or non-mission-critical lab equipment where cost drives selection |
| DS2502-E48+T&R | 1-Wire serial EEPROM; 1 Kbit capacity; no parallel interface or page-write capability | Requires bit-banged or dedicated 1-Wire master; incompatible with existing parallel bus designs | Consider only for new designs with minimal pin count and where serial topology simplifies cabling in distributed sensors |
Compared with AT28C256-20JC and DS2502-E48+T&R, the AT28C256-20LM/883 uniquely delivers military-qualified parallel interface performance, page-write efficiency, and hermetic CLCC packaging-making it irreplaceable in legacy avionics upgrades where bus compatibility and environmental compliance are mandatory.
Availability
AT28C256-20LM/883 is available at Aetrix Electronics and suitable for avionics configuration storage, MIL-STD-1553 bus controller firmware, and tactical radio frequency synthesizer calibration requiring stable component supply across extended product lifecycles.
Supply support for AT28C256-20LM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a global semiconductor company specializing in microcontrollers, analog devices, and nonvolatile memory solutions for industrial, automotive, and aerospace markets.
The AT28C256 product line was designed specifically for high-reliability, military-temperature EEPROM applications requiring paged parallel architecture, hardware/software write protection, and JEDEC-standard pin compatibility with legacy SRAM-based systems.
FAQ
What is the maximum page write cycle time for AT28C256-20LM/883?
The AT28C256-20LM/883 has a maximum page write cycle time of 10 ms, as specified in Table 6-4 of DS20006344A. This applies to all 1–64-byte writes within a single page (defined by A6–A14). The device automatically manages internal timing after the first byte is latched, freeing the host bus for other tasks during the write period.
How does hardware write protection function on AT28C256-20LM/883?
AT28C256-20LM/883 implements hardware write protection via VCC-sense (inhibits writes below 3.8 V typical), a 5 ms power-on delay after VCC stabilization, noise filtering rejecting <15 ns pulses on WE/CE, and standard logic-level inhibition (holding OE low, CE high, or WE high). These features operate independently of software data protection and are active at power-up.
Can AT28C256-20LM/883 be used in place of standard SRAM in existing designs?
Yes, AT28C256-20LM/883 is accessed like Static RAM for reads and writes without external components, supporting identical CE/OE/WE control logic. However, write cycles require explicit end-of-write detection via DATA Polling or Toggle Bit-unlike SRAM-so timing-critical systems must implement polling or timeout handling before subsequent accesses.
What package type is used for AT28C256-20LM/883?
AT28C256-20LM/883 uses a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12, with pins 1 and 17 designated "Don't Connect." This hermetically sealed package meets military reliability standards for thermal shock, moisture resistance, and long-term stability in harsh environments.
Is software data protection enabled by default on AT28C256-20LM/883?
No, software data protection (SDP) is disabled by default on AT28C256-20LM/883. It must be explicitly enabled using the three-byte unlock sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h). Once enabled, SDP remains active through power cycles until the disable sequence (AAh/55h/80h/AAh/20h/55h/2AAAh) is issued.
AT28C256-20LM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28C256-20LM/883 FAQ
1.How can I place an order for AT28C256-20LM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256-20LM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256-20LM/883 reliable?
The price and inventory of AT28C256-20LM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256-20LM/883 is usually 5 days.
3.What payment methods are accepted for AT28C256-20LM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256-20LM/883 transactions.
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4.How is shipping managed for AT28C256-20LM/883?
AT28C256-20LM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256-20LM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256-20LM/883?
For technical support, including AT28C256-20LM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256-20LM/883 requirements.
6.How does Aetrix verify that AT28C256-20LM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C256-20LM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256-20LM/883 meets industry standards.
7.What is the process for return or replacement of AT28C256-20LM/883?
All AT28C256-20LM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256-20LM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256-20LM/883 part is unused and in its original packaging.
Return procedure for AT28C256-20LM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C256-20LM/883 Tags

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M24C02-WMN6TP
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M24C02-FMC6TG
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AT24CS02-SSHM-T
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93LC46BT-I/OT
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