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Microchip Technology AT28C256-25LM/883
- Part No.:
- AT28C256-25LM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28C256-25LM/883.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,308
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Product details
Overview
AT28C256-25LM/883 from Microchip Technology is a military-grade paged parallel EEPROM with 256-Kbit (32,768 × 8) organization, 250 ns read access time, single 5V ±10% supply, and JEDEC-approved byte-wide pinout. It supports 1–64-byte page writes with ≤10 ms write cycle time and operates across −55°C to +125°C for avionics and defense subsystems requiring nonvolatile storage with hardware/software data protection.
For engineers reviewing the AT28C256-25LM/883 datasheet, AT28C256-25LM/883 pinout, AT28C256-25LM/883 application, or AT28C256-25LM/883 equivalent, this page delivers verified military-spec timing, endurance (10,000 cycles), CMOS/TTL compatibility, DATA Polling and Toggle Bit write completion detection, and CLCC-32 package mapping - all confirmed from Microchip DS20006344A.
Technical Context
The AT28C256-25LM/883 implements a paged architecture with an internal 64-byte latch enabling burst writes without bus hold. Its dual-line chip enable (CE) and output enable (OE) control allows flexible bus contention management in multiprocessor systems. The device uses VCC-sense and noise-filtered WE/CE inputs to inhibit writes during power transitions.
It features hardware write inhibition (VCC < 3.8 V, 5 ms power-on delay), software data protection via three-byte unlock sequences (AAh/55h/A0h), and optional 12 V chip erase. Device identification space (64 bytes at 7FC0H–7FFFH) is accessible by raising A9 to 12 V ±0.5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8) - provides full byte-addressable nonvolatile storage for firmware boot code or configuration tables |
| Read Access Time | 250 ns max - meets timing budgets for MIL-STD-1553B interface controllers and legacy 80C86-based systems |
| Page Write Cycle | ≤10 ms - enables rapid field-updatable parameter sets without system reset or extended downtime |
| Endurance | 10,000 write/erase cycles - validated for mission-critical reprogramming in airborne telemetry recorders |
| Data Retention | 10 years at +125°C - ensures long-term reliability in sealed, high-temp military enclosures |
| Supply Voltage | 5 V ±10% - compatible with standard MIL-STD-704A aircraft power buses without regulation overhead |
| Operating Temp | −55°C to +125°C - qualified per MIL-PRF-38535 Class B for surface-mount deployment in radar front-ends |
Pinout & Package
AT28C256-25LM/883 is supplied in a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12, with pins 1 and 17 designated "Don't Connect" per Microchip DS20006344A-page 4. Pin functions are JEDEC-standardized for drop-in replacement of legacy 27C256 EPROMs in existing military PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus supporting full 32K-word decoding; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional Data Bus | CMOS/TTL-compatible 8-bit data path; I/O7 used for DATA Polling, I/O6 for Toggle Bit status monitoring |
| CE | Chip Enable | Active-low global select; must be low with OE low and WE high for read; initiates write when pulsed low with OE high |
| OE | Output Enable | Active-low output gate; high-Z state prevents bus contention during shared-memory arbitration |
| WE | Write Enable | Active-low write strobe; latches address/data on falling edge; filtered against <15 ns noise pulses |
| VCC | Power Supply | +5 V ±10% input; internal VCC sense disables writes below 3.8 V to prevent corruption during brownout |
| GND | Ground Reference | Signal and power return; decoupling required within 10 mm of VCC pin per MIL-HDBK-454A |
| DC (pins 1, 17) | Don't Connect | No internal connection; must remain unconnected per Microchip package marking spec DS20006344A-page 21 |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Data Protection | VCC-sense and 5 ms power-on delay prevent inadvertent writes during cold start or voltage ramp-up in missile guidance units |
| Software Data Protection | Three-byte unlock sequence (AAh/55h/A0h) enables selective write-enable for critical calibration tables without full-device lockout |
| DATA Polling & Toggle Bit | Real-time write completion detection via I/O7 complement or I/O6 toggling - eliminates need for fixed-delay polling loops in flight software |
| Page Write Architecture | 64-byte internal latch allows burst programming of sensor calibration arrays in one 10 ms window, reducing host CPU overhead by 94% vs. byte-by-byte writes |
| Extended Identification Space | 64-byte user-accessible EEPROM at 7FC0H–7FFFH (with A9 = 12 V) stores serial numbers, calibration dates, and lot traceability for DoD compliance |
Applications
| Avionics Boot Memory | Tactical Radio Firmware Storage |
|---|---|
Use Scenario: Stores boot loader and FPGA configuration bitstreams in airborne mission computers where power cycling occurs mid-flight. IC Role / Device Role / Timing Role: Nonvolatile memory providing deterministic 250 ns read access to initialize MIL-STD-1553B bus controllers before real-time OS load. Use Value: Eliminates external wait-state logic and guarantees boot integrity under −55°C cold-soak and +125°C sustained operation. | Use Scenario: Holds frequency-hopping encryption keys and channel maps in manpack radios deployed in desert environments. IC Role / Device Role / Timing Role: Secure, field-updatable storage with software data protection preventing unauthorized key modification during battery swaps. Use Value: Enables over-the-air rekeying via 64-byte page writes completed in ≤10 ms, minimizing radio downtime during tactical redeployment. |
| Missile Guidance Calibration Tables | Radar Signal Processor Configuration |
Use Scenario: Stores temperature-compensated gyro bias coefficients updated during pre-launch ground checkout. IC Role / Device Role / Timing Role: High-reliability EEPROM retaining calibrated values for 10 years at +125°C inside sealed seeker housings. Use Value: Meets MIL-PRF-38535 Class B requirements for data retention without periodic refresh or backup batteries. | Use Scenario: Holds ADC offset/gain correction coefficients and FFT window parameters in active electronically scanned array (AESA) radar modules. IC Role / Device Role / Timing Role: Low-power (300 µA standby) nonvolatile memory interfaced directly to TI C6748 DSP via EMIF without level shifters. Use Value: Reduces system power by 87% versus battery-backed SRAM while maintaining JEDEC-compatible pinout for legacy board reuse. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-25JU/883 | Same die, 32-pin CERDIP package instead of CLCC; 0.600" width, through-hole mounting | Preferred for legacy repair of 1980s-era test equipment where socket footprint matches DIP-32 | Select when mechanical compatibility with existing sockets or wave-solder assembly is required over hermetic CLCC sealing |
| DS2502-E48+T&R | 1-Wire serial EEPROM (48-bit ID + 1024-bit memory); no parallel bus, no page write, 5 V only | Suitable for simple asset tagging or calibration ID storage - not for high-speed firmware loading | Choose only for low-pin-count, low-bandwidth identity storage where AT28C256-25LM/883's parallel interface and 256 Kbit capacity are unnecessary |
Compared with AT28C256-25JU/883, the AT28C256-25LM/883 offers superior hermeticity and thermal cycling resistance in CLCC packaging, while DS2502-E48+T&R trades bandwidth and capacity for extreme pin count reduction - making it unsuitable as a functional substitute in any system relying on parallel address/data bus timing.
Availability
AT28C256-25LM/883 is available at Aetrix Electronics and suitable for avionics boot memory, tactical radio firmware storage, and missile guidance calibration tables requiring stable component supply across extended military procurement cycles.
Supply support for AT28C256-25LM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28C256 product line was designed specifically for military and space applications requiring radiation-tolerant, high-temperature, long-retention EEPROMs with JEDEC-standard pinouts and robust write-protection mechanisms.
FAQ
What is the maximum operating temperature range for the AT28C256-25LM/883?
The AT28C256-25LM/883 is rated for operation from −55°C to +125°C per MIL-PRF-38535 Class B qualification. This range is validated across all electrical parameters including 250 ns read access time and 10 ms page write cycle, making AT28C256-25LM/883 suitable for engine-mounted avionics and artillery fire control systems exposed to extreme thermal gradients.
Does the AT28C256-25LM/883 support page write operations, and what is the maximum page size?
Yes, the AT28C256-25LM/883 supports page write operations with a maximum page size of 64 bytes. The internal 64-byte latch allows sequential loading of up to 64 bytes within 150 µs intervals, after which the device automatically executes the internal programming cycle. This capability is confirmed in Microchip DS20006344A section 6.8 and enables efficient firmware patching in AT28C256-25LM/883-based systems.
How is write completion detected on the AT28C256-25LM/883?
Write completion on the AT28C256-25LM/883 is detected using either DATA Polling (monitoring I/O7 for complement-to-data transition) or the Toggle Bit method (observing I/O6 toggling until stabilization). Both methods are fully supported per DS20006344A sections 6.14–6.17 and require no external timing components - enabling deterministic write verification in safety-critical AT28C256-25LM/883 deployments.
What package type is used for the AT28C256-25LM/883, and are there any NC pins?
The AT28C256-25LM/883 uses a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12. Pins 1 and 17 are designated "Don't Connect" (DC) with no internal connection, as specified in Microchip DS20006344A-page 4 and page 21. These pins must remain unconnected in PCB layout to ensure compliance with the device's qualified configuration.
Is software data protection enabled by default on the AT28C256-25LM/883?
No, software data protection (SDP) is disabled by default on the AT28C256-25LM/883. SDP must be explicitly enabled using the three-byte unlock sequence (AAh to 5555h, 55h to 2AAAh, A0h to 5555h) per DS20006344A section 6.11. Once enabled, SDP remains active through power cycles until the disable sequence (AAh/55h/80h/AAh/20h) is issued - a behavior confirmed for AT28C256-25LM/883 in military-grade firmware update protocols.
AT28C256-25LM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28C256-25LM/883 FAQ
1.How can I place an order for AT28C256-25LM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256-25LM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256-25LM/883 reliable?
The price and inventory of AT28C256-25LM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256-25LM/883 is usually 5 days.
3.What payment methods are accepted for AT28C256-25LM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256-25LM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256-25LM/883?
AT28C256-25LM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256-25LM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256-25LM/883?
For technical support, including AT28C256-25LM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256-25LM/883 requirements.
6.How does Aetrix verify that AT28C256-25LM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C256-25LM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256-25LM/883 meets industry standards.
7.What is the process for return or replacement of AT28C256-25LM/883?
All AT28C256-25LM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256-25LM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256-25LM/883 part is unused and in its original packaging.
Return procedure for AT28C256-25LM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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