Microchip Technology AT28C256-25LM/883-815
- Part No.:
- AT28C256-25LM/883-815
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-CLCC
- Datasheet:
-
AT28C256-25LM/883-815.pdf
- Description:
- IC EEPROM 256KBIT PARALLEL 32LCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C256-25LM/883-815 from Microchip Technology is a military-grade paged parallel EEPROM with 256-Kbit (32,768 × 8) organization, 250 ns read access time, single 5V ±10% supply, and JEDEC-approved byte-wide pinout. It supports 1–64-byte page writes with internal latching and automatic timing, and is used in avionics data logging, missile guidance firmware storage, and radiation-tolerant embedded control systems.
For engineers reviewing the AT28C256-25LM/883-815 datasheet, AT28C256-25LM/883-815 pinout, AT28C256-25LM/883-815 application, or AT28C256-25LM/883-815 equivalent, this page delivers verified military-spec electrical parameters, MIL-STD-883 Class B packaging details, page write timing constraints, hardware/software data protection logic, and direct alternatives for high-reliability system design.
Technical Context
The AT28C256-25LM/883-815 implements a CMOS-based paged EEPROM architecture with a 64-byte internal page register, enabling burst writes without external address/data bus hold. Its dual-line chip enable (CE) and output enable (OE) control allows precise bus contention management in multi-master military backplanes.
It features VCC sense circuitry that inhibits writes below 3.8 V, a 5 ms power-on delay timer, noise filtering on WE/CE inputs (<15 ns rejection), and optional software data protection using a three-byte unlock sequence (AAh/55h/A0h). Device identification space (7FC0h–7FFFh) is accessible via A9 = 12 V ±0.5 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8) - supports full firmware image storage for microcontrollers in guided weapon subsystems |
| Read access time | 250 ns max - meets timing budgets for MIL-STD-1553B bus interface controllers operating at 1 MHz |
| Page write cycle | 10 ms max - enables rapid field updates of configuration tables without system reset |
| VCC supply | 5 V ±10% - compatible with legacy military power rails and eliminates need for dedicated voltage regulators |
| Endurance | 10,000 write cycles - validated per MIL-STD-883 Method 1033 for sustained operation in ground vehicle ECU reprogramming |
| Data retention | 10 years at +125°C - certified for long-term deployment in uncooled airborne electronics enclosures |
| Operating temperature | −55°C to +125°C - qualified to MIL-PRF-38535 Class B for extended mission profiles |
Pinout & Package
AT28C256-25LM/883-815 is supplied in a 32-pad Ceramic Leadless Chip Carrier (CLCC) package compliant with MIL-STD-1835 C-12, with pins 1 and 17 designated "Don't Connect" per datasheet DS20006344A-page 4. The package is hermetically sealed, rated for 100% burn-in and 100% parametric testing under MIL-STD-883.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional data bus | CMOS/TTL-compatible 8-bit parallel interface; I/O7 provides DATA Polling status, I/O6 provides Toggle Bit status |
| CE | Chip Enable | Active-low primary device select; must be low for read/write; combined with OE/WE to determine operating mode per Table 6-1 |
| OE | Output Enable | Active-low output gate; high-Z when high, even if CE is low - prevents bus contention during shared-memory arbitration |
| WE | Write Enable | Active-low write strobe; falling edge latches address/data; initiates byte or page write when CE low and OE high |
| VCC | Power supply | +5 V ±10% input; internal VCC sense disables writes below 3.8 V to prevent corruption during brownout |
| GND | Ground reference | Signal return path; decoupling capacitor (0.1 µF ceramic) required within 10 mm of VCC/GND pins per MIL-HDBK-454 |
| DC (pins 1, 17) | Don't Connect | No internal connection; must remain floating - solder mask coverage required per MIL-STD-2000A paragraph 4.5.2 |
Key Features
| Feature | Design Value |
|---|---|
| Hardware data protection | VCC sense + 5 ms power-on delay + noise-filtered WE/CE inputs prevent spurious writes during power sequencing in aircraft power distribution units |
| Software data protection (SDP) | Three-byte unlock sequence (AAh/55h/A0h) enables selective firmware partition locking - critical for DO-254 Level A avionics partitioning |
| DATA Polling & Toggle Bit | I/O7 complement-read and I/O6 toggle provide deterministic, bus-compatible write completion detection without requiring external timers or interrupts |
| Page write capability | 64-byte internal latch allows sequential loading of calibration tables or mission parameters in ≤150 µs intervals - reduces host CPU overhead by >90% vs. byte writes |
| Device identification area | 64-byte reserved zone (7FC0h–7FFFh) accessible at 12 V on A9 - used for MIL-STD-130 UID tagging and field-replaceable unit traceability |
Applications
| Avionics Flight Control Memory | Tactical Radio Firmware Storage |
|---|---|
Use Scenario: Storing real-time flight envelope limit tables and sensor calibration coefficients in fly-by-wire ECUs. IC Role / Device Role / Timing Role: Nonvolatile memory mapped into microcontroller address space; accessed as SRAM-equivalent during boot and runtime parameter lookup. Use Value: 250 ns read access ensures <1 µs latency for stall margin calculations; 10,000-cycle endurance supports 20+ years of depot-level recalibration. |
Use Scenario: Holding encrypted waveform definitions and cryptographic keys in SATCOM radios deployed on naval vessels. IC Role / Device Role / Timing Role: Secure configuration store with hardware/software write protection; isolated from main processor via dedicated address decode. Use Value: 12 V A9 programming enables UID embedding per MIL-STD-130; SDP prevents accidental overwrites during RF firmware upgrades. |
| Missile Guidance System Boot ROM | Armored Vehicle Diagnostic Logger |
Use Scenario: Hosting immutable boot loader and self-test routines in solid-fuel missile guidance computers exposed to 20,000 g launch shock. IC Role / Device Role / Timing Role: Primary boot memory accessed directly by ASIC boot ROM controller; no external glue logic required. Use Value: Hermetic CLCC package withstands MIL-STD-810H vibration/shock; −55°C to +125°C range ensures reliability across desert-to-arctic operational envelopes. |
Use Scenario: Recording engine fault codes and CAN bus diagnostics in tracked vehicle engine control modules operating in sand/dust environments. IC Role / Device Role / Timing Role: Local nonvolatile log buffer; written in 64-byte pages during idle bus cycles to minimize impact on real-time CAN traffic. Use Value: Page write reduces write time by 63× vs. byte mode; 300 µA standby current extends battery-backed logging duration to >72 hours. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-25DM/883 | 32-lead CERDIP package instead of 32-pad CLCC; identical electrical specs and MIL-STD-883 Class B qualification | Preferred where through-hole mounting and manual rework are required in legacy repair depots | Select when board layout uses DIP footprints or requires hand-solder rework capability |
| DS2502-E48+T&R | 1-Wire serial interface (not parallel); 1024-bit EEPROM; no page write; lower endurance (100k cycles) | Suitable only for low-bandwidth ID tagging (e.g., module serialization), not firmware storage | Choose only for simple UID/traceability functions where pin count reduction outweighs speed and capacity loss |
Compared with AT28C256-25DM/883, the AT28C256-25LM/883-815 offers superior thermal cycling performance in surface-mount assemblies; versus DS2502-E48+T&R, it delivers 256× more capacity, parallel access speed, and deterministic write timing essential for safety-critical firmware updates.
Availability
AT28C256-25LM/883-815 is available at Aetrix Electronics and suitable for avionics flight control, tactical radio firmware storage, missile guidance system boot ROM, and armored vehicle diagnostic logger applications requiring stable component supply across extended product lifecycles.
Supply support for AT28C256-25LM/883-815 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28C256 product line was developed to deliver radiation-tolerant, high-endurance parallel EEPROMs meeting MIL-PRF-38535 Class B requirements for mission-critical embedded systems.
FAQ
What is the maximum page write time specification for AT28C256-25LM/883-815?
The AT28C256-25LM/883-815 has a maximum page write cycle time of 10 ms, as specified in Table 6-4 of datasheet DS20006344A. This applies to all 1–64-byte writes within a single page (defined by A6–A14). The device automatically manages internal timing after the final WE pulse, eliminating need for external wait-state generation. This 10 ms value is guaranteed across the full −55°C to +125°C operating range.
Does AT28C256-25LM/883-815 support both hardware and software write protection?
Yes, AT28C256-25LM/883-815 implements dual-layer write protection. Hardware protection includes VCC sensing (inhibits writes below 3.8 V), 5 ms power-on delay, noise filtering on WE/CE inputs, and standard CE/OE/WE logic gating. Software protection is enabled via a three-byte unlock sequence (AAh/55h/A0h) written to specific addresses, which must precede any protected write. Both mechanisms operate independently and concurrently.
What package type is used for AT28C256-25LM/883-815 and what are its key mechanical qualifications?
AT28C256-25LM/883-815 uses a 32-pad Ceramic Leadless Chip Carrier (CLCC) package per MIL-STD-1835 C-12. It is hermetically sealed, qualified to MIL-STD-883 Method 1014 for leak testing, and subjected to 100% burn-in per Method 1015. Pins 1 and 17 are "Don't Connect" and must remain unconnected per datasheet DS20006344A-page 4. The package meets MIL-PRF-38535 Class B screening requirements.
How is end-of-write detection implemented in AT28C256-25LM/883-815?
AT28C256-25LM/883-815 provides two independent end-of-write detection methods: DATA Polling on I/O7 (complement of last written byte appears until completion) and Toggle Bit on I/O6 (toggles between 0/1 during write, stabilizes afterward). Both methods are bus-compatible and require no additional hardware. Polling can begin immediately after write initiation; toggle bit requires OE or CE toggling per Section 6.17. Neither method affects timing or reliability.
What is the endurance rating and data retention specification for AT28C256-25LM/883-815?
AT28C256-25LM/883-815 is rated for 10,000 write/erase cycles and 10 years of data retention at +125°C, as confirmed in Section 4.3 and Section 3 of datasheet DS20006344A. These values are validated per MIL-STD-883 Method 1033 (endurance) and Method 1008 (retention) and apply to the full military temperature range. The device uses advanced CMOS process technology with error correction to achieve these figures under Class B screening.
AT28C256-25LM/883-815 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-CLCC
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-LCC (11.43x13.97)
AT28C256-25LM/883-815 FAQ
1.How can I place an order for AT28C256-25LM/883-815 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256-25LM/883-815 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256-25LM/883-815 reliable?
The price and inventory of AT28C256-25LM/883-815 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256-25LM/883-815 is usually 5 days.
3.What payment methods are accepted for AT28C256-25LM/883-815?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256-25LM/883-815 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256-25LM/883-815?
AT28C256-25LM/883-815 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256-25LM/883-815 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256-25LM/883-815?
For technical support, including AT28C256-25LM/883-815 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256-25LM/883-815 requirements.
6.How does Aetrix verify that AT28C256-25LM/883-815 is sourced from the original manufacturer or authorized distributors?
All AT28C256-25LM/883-815 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256-25LM/883-815 meets industry standards.
7.What is the process for return or replacement of AT28C256-25LM/883-815?
All AT28C256-25LM/883-815 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256-25LM/883-815, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256-25LM/883-815 part is unused and in its original packaging.
Return procedure for AT28C256-25LM/883-815:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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