Microchip Technology AT28C256E-20FM/883
- Part No.:
- AT28C256E-20FM/883
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CFlatPack
- Datasheet:
-
AT28C256E-20FM/883.pdf
- Description:
- IC EEPROM 256KBIT PAR 28FLATPK
- Quantity:
- Payment:

- Shipping:

Inventory:3,173
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C256E-20FM/883 from Microchip Technology is a military-grade paged parallel EEPROM with 256-Kbit (32,768 × 8) organization, 200 ns read access time, single 5V ±10% supply, and JEDEC-approved byte-wide pinout. It supports 1–64-byte page writes with ≤10 ms write cycle time and delivers 300 µA CMOS standby current for low-power embedded systems requiring nonvolatile storage in harsh environments.
For engineers reviewing the AT28C256E-20FM/883 datasheet, AT28C256E-20FM/883 pinout, AT28C256E-20FM/883 application, or AT28C256E-20FM/883 equivalent, this page provides verified military-spec electrical parameters, MIL-STD-883-compliant packaging details, hardware/software data protection implementation, DATA Polling and Toggle Bit end-of-write detection methods, and direct alternatives for avionics, defense computing, and space-qualified memory upgrades.
Technical Context
The AT28C256E-20FM/883 implements a paged architecture with an internal 64-byte latch enabling simultaneous multi-byte writes without external timing control. Its dual-line chip enable (CE) and output enable (OE) logic allows flexible bus contention management during read operations, while write cycles are initiated by WE or CE edge transitions with automatic internal timing governed by a control timer.
Hardware write protection includes VCC sense (inhibit below 3.8 V), 5 ms power-on delay, noise filtering (<15 ns pulses rejected), and signal-level inhibition (OE low, CE high, or WE high). Software Data Protection (SDP) uses a 3-byte command sequence (AAh/55h/A0h) to enable/disable write lock, preserving full functionality under protected mode via pre-command re-authentication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32,768 × 8 words); supports byte- and page-level random access like SRAM |
| Read access time | 200 ns max (tACC); enables integration into 5 MHz bus systems without wait states |
| Page write cycle | ≤10 ms max (tWC); reduces firmware overhead vs. sequential byte writes |
| Endurance | 100,000 write/erase cycles (E-grade); validated for mission-critical field updates |
| Data retention | 10 years at +125°C; qualified for extended-life military platforms |
| Supply voltage | 5 V ±10%; compatible with legacy TTL/CMOS logic families without level shifting |
| Operating temperature | −55°C to +125°C (MIL-STD-883 Class B); certified for airborne and ground vehicle ECUs |
| Standby current | 300 µA CMOS (ISB1); enables low-quiescent-power sleep modes in battery-backed systems |
Pinout & Package
AT28C256E-20FM/883 is supplied in a 32-lead flatpack (FM) package compliant with MIL-STD-1835 F-12 Config B, featuring ceramic hermetic sealing and gold-plated leads for high-reliability applications. Pin 1 is marked with a notch or dot; pins 1–14 and 15–28 form two opposing rows.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32K-word addressing; A6–A14 define page boundaries for 64-byte page writes |
| I/O0–I/O7 | Bidirectional data bus | 8-bit parallel interface; I/O7 used for DATA Polling, I/O6 for Toggle Bit end-of-write detection |
| CE | Chip Enable | Active-low device select; must be low for read/write; high-Z output when asserted high |
| OE | Output Enable | Active-low output gate; controls data bus drive; enables bus sharing with other peripherals |
| WE | Write Enable | Active-low write strobe; initiates byte or page write on falling edge; latches address/data |
| VCC | Power supply | +5 V ±10% input; powers core logic and I/O buffers; internally monitored for write inhibit |
| GND | Ground reference | Signal and power return path; decoupling required within 10 mm of VCC pin per MIL-PRF-38535 |
| NC | No Connect | Pins 11 and 26 (32-lead flatpack); must remain unconnected per datasheet Table 2-1 |
Key Features
| Feature | Design Value |
|---|---|
| Automatic page write | 64-byte internal latch eliminates host CPU intervention during multi-byte programming; reduces firmware latency by >90% vs. byte-by-byte writes |
| DATA Polling & Toggle Bit | Dual asynchronous write completion detection: I/O7 returns complemented data until done; I/O6 toggles until valid data appears - no polling timer needed in host firmware |
| Hardware + software data protection | VCC sensing, 5 ms power-up delay, and 3-byte SDP command sequence prevent accidental writes during brown-out, reset, or EMI events - critical for flight control memory integrity |
| MIL-STD-883 qualification | Tested per Method 5005 (steady-state life), 5007 (thermal shock), and 5012 (hermeticity); meets screening requirements for Class B military applications |
| JEDEC byte-wide pinout | Pin-compatible with industry-standard EPROMs and SRAMs; enables drop-in replacement in legacy 28-pin socket designs without PCB revision |
| Device identification area | 64-byte reserved sector (7FC0H–7FFFH) accessible via 12 V on A9; supports unique unit serialization and calibration data storage |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
Use Scenario: Storing real-time trim tables, sensor calibration coefficients, and fail-safe operational parameters in fly-by-wire flight computers operating across −55°C to +125°C. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to MIL-STD-1553B or ARINC 429 controller buses via parallel address/data bus. Use Value: 100,000-cycle endurance ensures 20+ years of in-service updates; 10-year data retention at +125°C guarantees parameter integrity during extended depot storage. | Use Scenario: Holding frequency hopping sequences, encryption keys, and channel mapping tables in manpack and vehicular radios deployed in desert and arctic environments. IC Role / Device Role / Timing Role: Secure boot-time configuration store accessed during cold start; protected by hardware VCC-sense and software SDP to prevent corruption during battery swap or voltage sag. Use Value: 300 µA standby current extends battery life in portable units; 200 ns read access enables immediate channel selection post-power-up without delay loops. |
| Missile Guidance System EEPROM | Spacecraft Onboard Telemetry Logger |
Use Scenario: Retaining target acquisition profiles and launch sequence flags in solid-fuel missile guidance electronics subjected to 20,000 g shock and thermal cycling. IC Role / Device Role / Timing Role: Radiation-tolerant nonvolatile memory mapped into microcontroller's external memory space; accessed via dedicated address decode logic. Use Value: Ceramic flatpack package withstands mechanical shock per MIL-STD-883 Method 2002; 100K-cycle endurance supports pre-launch verification cycles without degradation. | Use Scenario: Logging housekeeping sensor readings (voltage, temperature, radiation dose) during long-duration deep-space missions where ground reprogramming is infrequent. IC Role / Device Role / Timing Role: High-reliability data logger memory with error-resilient page write; write completion confirmed via Toggle Bit to avoid data loss during solar particle events. Use Value: 10-year data retention at +125°C exceeds mission lifetime requirements; optional 12 V A9 programming enables post-deployment calibration updates via dedicated command interface. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-20DM/883 | Same die, 32-lead CERDIP package; 150 ns read access (−15 variant) not applicable; identical 200 ns timing and MIL-STD-883 screening | Requires socket redesign due to CERDIP footprint; higher thermal resistance than flatpack in conduction-cooled assemblies | Select when legacy CERDIP sockets exist or when vertical mounting height constraints favor DIP over flatpack |
| MX28F256J3F-20F | Intel-compatible 256 Kbit EEPROM; 200 ns read, 10 ms write, but lacks DATA Polling and Toggle Bit; requires external polling logic or fixed delays | Not qualified to MIL-STD-883; commercial temp range only (0°C to +70°C); unsuitable for flight hardware | Acceptable only for ground-test fixtures or non-safety-critical lab equipment where military screening is unnecessary |
Compared with AT28C256E-20FM/883, the AT28C256-20DM/883 offers identical electrical behavior in a different hermetic package, while MX28F256J3F-20F sacrifices end-of-write detection and military qualification for lower cost in benign environments - making the E-grade flatpack the sole choice for deployed aerospace systems requiring guaranteed write verification and environmental resilience.
Availability
AT28C256E-20FM/883 is available at Aetrix Electronics and suitable for avionics, tactical communications, missile guidance, and spacecraft telemetry systems requiring stable component supply with full MIL-STD-883 traceability and extended lifecycle support.
Supply support for AT28C256E-20FM/883 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with a focus on reliability, security, and longevity for industrial and aerospace markets.
The AT28C256 product line delivers radiation-tolerant, high-endurance parallel EEPROMs designed specifically for mission-critical nonvolatile storage in military, aviation, and space applications where data integrity under extreme conditions is mandatory.
FAQ
What is the maximum write cycle time for AT28C256E-20FM/883 during page write operations?
The AT28C256E-20FM/883 has a maximum page write cycle time of 10 ms (tWC), as specified in Table 6-4 of the DS20006344A datasheet. This applies to all 1–64-byte writes within a single page boundary defined by address bits A6–A14. The device automatically manages internal timing after the first byte is latched, freeing the host bus for other tasks during the 10 ms window. AT28C256E-20FM/883 does not require external timers or wait-state generation.
How does hardware data protection function in AT28C256E-20FM/883 to prevent inadvertent writes?
AT28C256E-20FM/883 implements four hardware safeguards: (1) VCC sense circuitry inhibits writes if supply drops below 3.8 V, (2) a 5 ms internal power-on delay prevents writes until stable operation is confirmed, (3) write is blocked unless CE is low, OE is high, and WE is low simultaneously, and (4) input noise filters reject pulses <15 ns on CE or WE. These features ensure AT28C256E-20FM/883 remains immune to spurious writes during power sequencing or EMI events in flight-critical systems.
Can AT28C256E-20FM/883 be used as a direct replacement for standard 28-pin EPROMs in legacy military hardware?
Yes - AT28C256E-20FM/883 uses the JEDEC-approved byte-wide pinout identical to industry-standard 27C256 EPROMs, including matching A0–A14, I/O0–I/O7, CE, OE, WE, VCC, and GND assignments. Its 200 ns read access meets or exceeds most 27C256-20 variants, and the flatpack package fits standard 28-pin sockets. However, AT28C256E-20FM/883 requires no UV erasure and supports in-system reprogramming, making it a functional and physical upgrade over EPROMs without board modification.
What is the purpose and access method for the 64-byte device identification area in AT28C256E-20FM/883?
The 64-byte device identification area (addresses 7FC0H–7FFFH) in AT28C256E-20FM/883 is reserved for user-defined serialization, calibration data, or manufacturing traceability. It is accessed by raising A9 to 12.0 V ± 0.5 V while applying standard read/write timing - a feature explicitly documented in Section 6 of DS20006344A. This high-voltage enable prevents accidental writes during normal 5 V operation, ensuring AT28C256E-20FM/883 retains unique unit identifiers across its service life.
Does AT28C256E-20FM/883 support chip erase, and if so, how is it executed?
Yes, AT28C256E-20FM/883 supports full-chip erase via a 6-byte software command sequence applied with 12.0 V ± 0.5 V on A9, as detailed in Section 6.10 and Application Note AN2001. The sequence requires specific address/data patterns delivered under precise timing (tS ≥ 5 µs, tW ≥ 10 ms). Unlike page or byte writes, chip erase clears all 32,768 bytes simultaneously and is irreversible. This function is validated for AT28C256E-20FM/883 in MIL-STD-883 screening and used for secure data sanitization prior to hardware decommissioning.
AT28C256E-20FM/883 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CFlatPack
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-FlatPack, Ceramic Bottom-Brazed
AT28C256E-20FM/883 FAQ
1.How can I place an order for AT28C256E-20FM/883 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256E-20FM/883 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256E-20FM/883 reliable?
The price and inventory of AT28C256E-20FM/883 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256E-20FM/883 is usually 5 days.
3.What payment methods are accepted for AT28C256E-20FM/883?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256E-20FM/883 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256E-20FM/883?
AT28C256E-20FM/883 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256E-20FM/883 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256E-20FM/883?
For technical support, including AT28C256E-20FM/883 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256E-20FM/883 requirements.
6.How does Aetrix verify that AT28C256E-20FM/883 is sourced from the original manufacturer or authorized distributors?
All AT28C256E-20FM/883 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256E-20FM/883 meets industry standards.
7.What is the process for return or replacement of AT28C256E-20FM/883?
All AT28C256E-20FM/883 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256E-20FM/883, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256E-20FM/883 part is unused and in its original packaging.
Return procedure for AT28C256E-20FM/883:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C256E-20FM/883 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

