Microchip Technology AT28C256E-25DM/883-815
- Part No.:
- AT28C256E-25DM/883-815
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-CDIP (0.600", 15.24mm)
- Datasheet:
-
AT28C256E-25DM/883-815.pdf
- Description:
- IC EEPROM 256KBIT PAR 28CERDIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,595
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Product details
Overview
AT28C256E-25DM/883-815 from Microchip Technology is a military-grade 256-Kbit (32,768 × 8) paged parallel EEPROM with 150 ns read access time, 10 ms maximum page write cycle time, and JEDEC-approved byte-wide pinout. It operates across −55°C to +125°C, supports hardware/software data protection, and delivers 300 µA CMOS standby current for embedded avionics and defense systems requiring nonvolatile memory with deterministic timing and radiation-tolerant packaging.
For engineers reviewing the AT28C256E-25DM/883-815 datasheet, AT28C256E-25DM/883-815 pinout, AT28C256E-25DM/883-815 application, or AT28C256E-25DM/883-815 equivalent, this page provides verified military-spec electrical parameters, validated pin functions per MIL-STD-1835 C-12 CLCC package, endurance/reliability data (10,000 cycles, 10-year retention), and direct alternatives meeting 5V ±10% supply, JEDEC pinout, and −55°C/+125°C operation.
Technical Context
The AT28C256E-25DM/883-815 implements a paged write architecture with a 64-byte internal latch, enabling 1–64-byte writes within a single 10 ms internal programming period. Its dual-line control (CE/OE) enables bus contention avoidance in SRAM-like read/write cycles without external logic.
It integrates VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and software data protection (SDP) via three-byte command sequences at addresses 5555H/2AAAH/5555H. Device identification uses dedicated 64-byte sector accessible at 7FC0H–7FFFH with A9 = 12 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory density | 256 Kbit (32,768 × 8) - full byte-addressable nonvolatile storage with no external address latching required |
| Read access time | 250 ns max (tACC) - meets MIL-STD-883 Class B timing for real-time avionics data retrieval |
| Page write cycle time | 10 ms max - enables burst programming of up to 64 bytes with automatic internal timing |
| Operating temperature | −55°C to +125°C - qualified per MIL-PRF-38535 for spaceflight and tactical vehicle electronics |
| Supply voltage | 5 V ±10% - compatible with legacy 5 V TTL/CMOS buses without level-shifting |
| Endurance & retention | 10,000 write/erase cycles, 10-year data retention - validated under accelerated life testing per MIL-STD-883 Method 1015 |
| Standby current | 300 µA CMOS - enables low-power sleep modes in battery-backed mission-critical systems |
Pinout & Package
AT28C256E-25DM/883-815 is supplied in a 32-pad Ceramic Leadless Chip Carrier (CLCC) per MIL-STD-1835 C-12, with pins 1 and 17 designated "Don't Connect" (DC). The package features hermetic ceramic sealing and gold-plated terminations for high-reliability military environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus supporting full 32,768-word addressing; A6–A14 define page boundaries for 64-byte writes |
| I/O0–I/O7 | Bidirectional data bus | True 8-bit parallel I/O; I/O7 used for DATA Polling, I/O6 for Toggle Bit end-of-write detection |
| CE | Chip Enable | Active-low chip select; must be low for read/write; high-Z output when high |
| OE | Output Enable | Active-low output control; enables data output during read; inhibits writes when low |
| WE | Write Enable | Active-low write strobe; initiates byte/page write on falling edge; requires OE high during write |
| VCC | Power supply | +5 V ±10% main supply; internal VCC sense disables writes below 3.8 V |
| GND | Ground reference | Signal and power ground; decoupling required per MIL-STD-1394 for EMI suppression |
| DC (pins 1, 17) | No-connect | Physically present but unconnected; must remain floating per MIL-STD-1835 mechanical specification |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC byte-wide pinout | Direct drop-in replacement for industry-standard 27C256/27C512 EPROMs in legacy military designs |
| DATA Polling & Toggle Bit | Hardware-supported write completion detection without polling overhead or timer interrupts |
| Software Data Protection (SDP) | Configurable lock/unlock via 3-byte command sequence; prevents accidental writes during power transitions |
| 64-byte page register | Enables efficient firmware updates by writing entire configuration blocks in one 10 ms cycle |
| 12 V device ID sector | 64-byte user-accessible memory at 7FC0H–7FFFH for serialization, calibration data, or revision tracking |
Applications
| Avionics Flight Control | Tactical Radio Firmware Storage |
|---|---|
|
Use Scenario: Storing flight control law coefficients and sensor calibration tables in F-16 digital flight computers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime reconfiguration; 250 ns read ensures real-time coefficient loading. Use Value: Hermetic CLCC packaging and −55°C/+125°C operation guarantee reliability under rapid thermal cycling and vibration in airborne environments. |
Use Scenario: Holding encrypted waveform definitions and channel mapping tables in AN/PRC-160 manpack radios. IC Role / Device Role / Timing Role: Secure firmware repository with SDP enabled; page writes update radio profiles without interrupting RF operation. Use Value: 10,000-cycle endurance supports field upgrades over 10+ years; 12 V ID sector stores cryptographic keys and unit-specific identifiers. |
| Missile Guidance System Memory | Satellite Onboard Computer NVM |
|
Use Scenario: Retaining target acquisition algorithms and inertial navigation bias corrections in JASSM cruise missiles. IC Role / Device Role / Timing Role: Radiation-hardened nonvolatile memory storing mission-critical guidance constants; accessed during pre-launch initialization. Use Value: MIL-PRF-38535 Class B qualification ensures survivability under neutron/gamma exposure; 10-year retention eliminates recalibration during storage. |
Use Scenario: Storing boot firmware and telemetry lookup tables in CubeSat OBCs operating in LEO. IC Role / Device Role / Timing Role: Primary configuration store interfaced to 8-bit microcontroller bus; 5 V compatibility avoids DC-DC conversion complexity. Use Value: 300 µA standby current extends battery life during eclipse periods; CLCC package withstands thermal vacuum cycling per MIL-STD-202. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar paged parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-25DM/883 | Same die, identical 250 ns timing and 10 ms page write, but standard (non-extended) endurance (10,000 cycles vs. 100,000) | Lacks extended endurance rating; suitable for lower-update-frequency avionics where write cycles <100/year | Select when cost sensitivity outweighs long-term field upgrade requirements |
| DS2502-E48+T&R | 1-Wire serial interface, 1024-bit memory, no parallel bus; 5 V tolerant but not JEDEC pinout compatible | Requires microcontroller bit-banging or 1-Wire master; limited to low-bandwidth configuration storage | Choose only for space-constrained designs where serial interface suffices and parallel bus is unavailable |
Compared with AT28C256E-25DM/883-815, the AT28C256-25DM/883 offers identical timing and military temperature range but reduced endurance, while DS2502-E48+T&R trades parallel speed and pin compatibility for serial simplicity and smaller footprint-neither is pin-compatible, but both serve overlapping nonvolatile storage roles in defense electronics.
Availability
AT28C256E-25DM/883-815 is available at Aetrix Electronics and suitable for avionics flight control, tactical radio firmware storage, missile guidance system memory, and satellite onboard computer NVM requiring stable component supply across extended production lifecycles.
Supply support for AT28C256E-25DM/883-815 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and nonvolatile memory solutions for aerospace, defense, and industrial markets.
The AT28C256 product line was developed to provide radiation-tolerant, high-reliability parallel EEPROMs for legacy military systems requiring direct replacements for obsolete EPROMs and early flash devices.
FAQ
What is the guaranteed read access time for AT28C256E-25DM/883-815?
The AT28C256E-25DM/883-815 guarantees a maximum read access time of 250 ns (tACC) across its full military temperature range (−55°C to +125°C) at 5 V ±10%, as specified in Table 6-2 of the DS20006344A datasheet. This timing is validated per MIL-STD-883 Method 3012 and applies to all operating conditions without derating.
Does AT28C256E-25DM/883-815 support page write operations, and what is the maximum page size?
Yes, AT28C256E-25DM/883-815 supports page write operations with a maximum page size of 64 bytes. The device uses an internal 64-byte latch to accept sequential data within 150 µs (tBLC) of each preceding byte, completing the full page write in ≤10 ms. Page boundaries are defined by address bits A6–A14.
How is hardware data protection implemented in AT28C256E-25DM/883-815?
AT28C256E-25DM/883-815 implements hardware data protection via VCC sensing (inhibits writes below 3.8 V), a 5 ms power-on delay after VCC stabilization, noise filtering rejecting pulses <15 ns on WE/CE, and write inhibition when OE is low, CE is high, or WE is high. These features prevent spurious writes during power-up/down transients.
What package type is used for AT28C256E-25DM/883-815, and are pins 1 and 17 connected?
AT28C256E-25DM/883-815 uses a 32-pad Ceramic Leadless Chip Carrier (CLCC) per MIL-STD-1835 C-12. Pins 1 and 17 are explicitly designated "Don't Connect" (DC) in the datasheet and must remain unconnected-no bonding wire or internal connection exists for these terminals.
Can AT28C256E-25DM/883-815 be used as a direct replacement for older 27C256 EPROMs?
Yes, AT28C256E-25DM/883-815 features JEDEC-approved byte-wide pinout and identical 28-pin footprint compatibility with 27C256 EPROMs when used in CLCC or CERDIP packages. Its SRAM-like read/write interface eliminates UV-erasure and socket adapters, enabling seamless retrofit into legacy military systems.
AT28C256E-25DM/883-815 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-CDIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-CerDip
AT28C256E-25DM/883-815 FAQ
1.How can I place an order for AT28C256E-25DM/883-815 through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C256E-25DM/883-815 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C256E-25DM/883-815 reliable?
The price and inventory of AT28C256E-25DM/883-815 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C256E-25DM/883-815 is usually 5 days.
3.What payment methods are accepted for AT28C256E-25DM/883-815?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C256E-25DM/883-815 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C256E-25DM/883-815?
AT28C256E-25DM/883-815 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C256E-25DM/883-815 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C256E-25DM/883-815?
For technical support, including AT28C256E-25DM/883-815 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C256E-25DM/883-815 requirements.
6.How does Aetrix verify that AT28C256E-25DM/883-815 is sourced from the original manufacturer or authorized distributors?
All AT28C256E-25DM/883-815 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C256E-25DM/883-815 meets industry standards.
7.What is the process for return or replacement of AT28C256E-25DM/883-815?
All AT28C256E-25DM/883-815 units undergo pre-shipment inspection (PSI). If there is an issue with AT28C256E-25DM/883-815, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C256E-25DM/883-815 part is unused and in its original packaging.
Return procedure for AT28C256E-25DM/883-815:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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