Microchip Technology AT28C64-12JC
- Part No.:
- AT28C64-12JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28C64-12JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:3,206
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C64-12JC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 120 ns read access time, self-timed byte write (1 ms), CMOS/TTL-compatible I/O, and JEDEC-standard 28-pin PLCC package. It operates at 5V ±10%, supports commercial temperature range (0°C to 70°C), and delivers 30 mA active current and 100 µA standby current for embedded microcontroller data storage.
For engineers reviewing the AT28C64-12JC datasheet, AT28C64-12JC pinout, AT28C64-12JC application, or AT28C64-12JC equivalent, this device serves as a drop-in nonvolatile memory replacement for SRAM-based boot code or configuration storage where byte-level reprogrammability, READY/BUSY signaling, and DATA polling are required without external timing circuitry.
Technical Context
The AT28C64-12JC implements a parallel EEPROM architecture with internal address/data latching and an on-chip control timer that autonomously manages erase-before-write cycles. Its RDY/BUSY open-drain output and I/O7 DATA polling provide two hardware-synchronized methods to detect write completion.
It uses Atmel's proprietary nonvolatile technology with built-in error correction for enhanced endurance (10⁴ cycles) and 10-year data retention. The device includes VCC sense, power-on delay, and logic-level write inhibit to prevent inadvertent writes - all without requiring external voltage supervisors or timing components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - provides sufficient space for firmware patches, calibration tables, or device configuration in 8-bit microcontroller systems. |
| Read Access Time | 120 ns - enables direct interface with 8 MHz Z80, 6502, or 8051-family microprocessors without wait states. |
| Byte Write Time | 1 ms - allows background memory updates while CPU executes other tasks; no external write pulse generator needed. |
| Supply Voltage | 5V ±10% - compatible with standard TTL/CMOS logic rails and legacy industrial power supplies. |
| Operating Temperature | 0°C to 70°C - certified for commercial-grade embedded applications including point-of-sale terminals and instrumentation front-ends. |
| Standby Current | 100 µA - reduces system power budget in battery-backed or low-power sleep modes. |
| Endurance | 10,000 write/erase cycles - supports field-updatable parameters in devices requiring infrequent but reliable reconfiguration. |
Pinout & Package
AT28C64-12JC is housed in a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016AE, with pins 1 and 17 designated as "Don't Connect" (DC). Pin 1 is RDY/BUSY (open-drain), and pin 17 is NC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; compatible with 8085, Z80, and 68000 lower-address lines. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; electrically compatible with TTL and CMOS logic families without level shifters. |
| CE | Chip Enable | Active-low chip select; enables memory access only when asserted, allowing multi-device bus sharing. |
| OE | Output Enable | Active-low output gate; decouples data bus during reads to prevent contention when multiple peripherals share the bus. |
| WE | Write Enable | Active-low write strobe; initiates self-timed byte write on falling edge; latches address and data internally. |
| RDY/BUSY | Open-Drain Status Output | Pulled low during write cycle; supports wired-OR connection of multiple EEPROMs to a single status line. |
| VCC / GND | Power Supply | Single 5V supply with dedicated ground; no separate VPP or programming voltage required for normal operation. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed byte write | Eliminates need for external write pulse generators or timing controllers - simplifies PCB layout and firmware design. |
| READY/BUSY + DATA polling | Dual asynchronous write completion detection methods ensure robust integration across diverse microcontroller platforms. |
| VCC sense & power-on delay | Hardware-enforced write protection prevents corruption during brown-out or power ramp-up conditions. |
| JEDEC-standard pinout | Enables direct replacement of industry-standard 2764 EPROMs or 6264 SRAMs in existing socketed designs. |
| 32-byte ID area | User-accessible EEPROM segment at 1FE0H–1FFFH for serialization, calibration data, or board-specific identification. |
Applications
| Industrial HMI Panels | Legacy Microcontroller Boot Memory |
|---|---|
Use Scenario: Storing localized language strings, screen layouts, and user preferences in factory-floor HMIs with 8051 or Z80 controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via parallel bus during GUI initialization and runtime parameter updates. Use Value: Enables field-upgradable UI assets without firmware reflashing; 10⁴ endurance supports >5 years of daily configuration changes. |
Use Scenario: Holding bootloader code and hardware initialization routines for 8-bit microcontrollers in medical diagnostic equipment. IC Role / Device Role / Timing Role: Primary boot ROM replacement with byte-write capability for patching critical startup sequences post-deployment. Use Value: Eliminates need for UV-erasable EPROM sockets; 120 ns access ensures zero-wait-state execution on 8 MHz MCUs. |
| Point-of-Sale Terminal Settings | Test Equipment Calibration Storage |
Use Scenario: Retaining tax tables, receipt formatting rules, and merchant-specific settings across power cycles in retail POS terminals. IC Role / Device Role / Timing Role: Persistent parameter store interfaced directly to Intel 8085 or Motorola 68000-based mainboards. Use Value: 100 µA standby current extends battery backup life; RDY/BUSY signaling prevents premature read attempts after configuration writes. |
Use Scenario: Saving instrument-specific calibration coefficients and sensor offset values in benchtop multimeters and oscilloscopes. IC Role / Device Role / Timing Role: High-reliability nonvolatile storage accessed during power-up self-test and manual recalibration procedures. Use Value: 10-year data retention guarantees accuracy traceability; VCC-sense protection prevents accidental erasure during lab power fluctuations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-12JC | Enhanced version with improved data retention (100 years), tighter tACC spec (120 ns guaranteed), and updated DC characteristics. | Same pinout and timing; preferred for new designs requiring extended lifecycle compliance. | Select AT28C64B-12JC if long-term product continuity and higher reliability certification are required. |
| MX28LV640C-12JC | Macronix variant with identical 64K×8 organization, 120 ns access, and PLCC-32 package; supports same VCC range and JEDEC pinout. | Drop-in alternative with comparable endurance (10⁴ cycles); differs in chip-clear voltage (12 V vs. 12.5 V) and minor AC timing tolerances. | Choose MX28LV640C-12JC for dual-sourcing flexibility in cost-sensitive industrial programs. |
Compared with AT28C64-12JC, the AT28C64B-12JC offers longer data retention and tighter parametric guarantees, while MX28LV640C-12JC provides second-source assurance with identical footprint and functional behavior - both require no PCB or firmware changes for migration.
Availability
AT28C64-12JC is available at Aetrix Electronics and suitable for industrial HMI panels, legacy microcontroller boot memory, and point-of-sale terminal settings requiring stable component supply, long-lifecycle support, and verified drop-in compatibility with existing PLCC-32 footprints.
Supply support for AT28C64-12JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.
The AT28C64 series was designed as a pin-compatible, electrically erasable alternative to UV-erasable EPROMs and battery-backed SRAMs - targeting 8-bit system designers needing field-updatable, low-power, single-supply nonvolatile storage.
FAQ
What is the maximum operating frequency supported by AT28C64-12JC?
The AT28C64-12JC does not operate on a clock signal - it is an asynchronous parallel EEPROM. Its 120 ns read access time corresponds to reliable operation with microprocessors running up to approximately 8 MHz (assuming one memory cycle per instruction fetch). Timing is governed by CE, OE, and WE control signals rather than a system clock, making it compatible with Z80, 8051, 6502, and 68000 architectures without synchronization overhead.
Does AT28C64-12JC require a high-voltage programming supply?
No, AT28C64-12JC operates from a single 5V ±10% supply for both read and write operations. High voltage (12 V ±0.5 V) is required only for optional CHIP CLEAR or DEVICE IDENTIFICATION functions - standard byte writes use only VCC. This eliminates the need for charge pumps or external VPP generators, simplifying power design and reducing BOM cost compared to older EPROM or early EEPROM solutions.
How is write completion detected on AT28C64-12JC?
AT28C64-12JC provides two independent hardware methods: (1) RDY/BUSY pin (pin 1) goes low during write and releases high upon completion, supporting wired-OR status busing; (2) DATA polling reads I/O7 - it returns the complement of the written data until completion, then returns true data. Both methods allow the host processor to resume operation immediately after write finish without fixed delays or timeouts.
Can AT28C64-12JC replace a 2764 EPROM in an existing design?
Yes - AT28C64-12JC uses the JEDEC-approved byte-wide pinout identical to the 2764 EPROM (28-pin DIP), and its PLCC-32 variant (AT28C64-12JC) maintains the same logical pin mapping for A0–A12, I/O0–I/O7, CE, OE, and WE. No PCB redesign is needed; only firmware must be updated to manage write cycles using RDY/BUSY or DATA polling instead of UV-erase wait periods.
What is the purpose of the 32-byte ID area in AT28C64-12JC?
The 32-byte ID area (addresses 1FE0H–1FFFH) is a dedicated EEPROM segment accessible using standard read/write commands, but requires A9 raised to 12 V ±0.5 V during access. It is intended for permanent device serialization, manufacturing traceability codes, or calibration data storage - separate from main memory to avoid accidental overwrite during routine firmware updates.
AT28C64-12JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28C64-12JC FAQ
1.How can I place an order for AT28C64-12JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64-12JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64-12JC reliable?
The price and inventory of AT28C64-12JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64-12JC is usually 5 days.
3.What payment methods are accepted for AT28C64-12JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64-12JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64-12JC?
AT28C64-12JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64-12JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64-12JC?
For technical support, including AT28C64-12JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64-12JC requirements.
6.How does Aetrix verify that AT28C64-12JC is sourced from the original manufacturer or authorized distributors?
All AT28C64-12JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64-12JC meets industry standards.
7.What is the process for return or replacement of AT28C64-12JC?
All AT28C64-12JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64-12JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64-12JC part is unused and in its original packaging.
Return procedure for AT28C64-12JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C64-12JC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

