Microchip Technology AT28C64-12SI

Overview

AT28C64-12SI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 120 ns read access time, 1 ms fast byte write cycle, and industrial temperature range (–40°C to +85°C). It operates from a single 5V ±10% supply, supports READY/BUSY and DATA polling for write completion detection, and is used in embedded systems requiring nonvolatile configuration storage with microprocessor-compatible timing.

For engineers reviewing the AT28C64-12SI datasheet, AT28C64-12SI pinout, AT28C64-12SI application, or AT28C64-12SI equivalent, this page delivers verified electrical parameters, package-specific terminal mapping, real-world use cases in legacy control systems, and validated alternative parts with documented functional and timing differences.

Technical Context

The AT28C64-12SI implements self-timed byte write cycles using internal address/data latches and an on-chip control timer, eliminating external timing components. Its CMOS/TTL-compatible I/O allows direct interfacing with 8-bit microprocessors without level-shifting.

Write protection is enforced via VCC sense (inhibit below 3.8 V), 5 ms power-on delay, and triple-input logic (CE high, OE low, or WE high blocks writes). Chip Clear requires 12 V on OE and a 10 ms WE pulse, while device identification uses 32 bytes at addresses 1FE0H–1FFFH with A9 raised to 12 V.

Key Specifications

Pinout & Package

AT28C64-12SI is supplied in a 28-lead SOIC (Small Outline Integrated Circuit) package per JEDEC MS-012, with 300-mil body width and gull-wing leads. Pin 1 is RDY/BUSY (open-drain), active-low during write operations.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64-12SI, AT28C64B-12SI offers superior data retention and tighter write consistency for mission-critical deployments, while MX28C64PC-12 provides faster write capability without layout changes-making both viable alternatives depending on whether longevity or speed is the primary design constraint.

Availability

AT28C64-12SI is available at Aetrix Electronics and suitable for industrial control systems, legacy telecom infrastructure upgrades, and medical device recalibration requiring stable component supply and long-lifecycle support.

Supply support for AT28C64-12SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C64 series was designed as a drop-in parallel EEPROM solution for 8-bit microprocessor systems needing reliable, low-power, field-programmable nonvolatile storage with minimal external support circuitry.

FAQ

What is the maximum read access time specified for the AT28C64-12SI?

The AT28C64-12SI has a maximum read access time of 120 ns under commercial and industrial temperature ranges at 5 V supply. This value is guaranteed across the full operating temperature range (–40°C to +85°C) and defines the minimum time between address valid and stable data on I/O0–I/O7. The "12" in the part number directly denotes this 120 ns speed grade, making AT28C64-12SI suitable for systems previously using 120 ns SRAM without timing adjustments.

Does the AT28C64-12SI support both READY/BUSY and DATA polling for write completion detection?

Yes, the AT28C64-12SI supports both methods. The RDY/BUSY pin (Pin 1) is an open-drain output that pulls low during write cycles and releases upon completion. Simultaneously, DATA polling is implemented by reading I/O7: it returns the complement of the written data until the write finishes, then asserts true data. Both mechanisms are fully functional in the AT28C64-12SI and require no external components, giving designers flexibility in interrupt-driven or polling-based firmware architectures.

What package type and lead count does the AT28C64-12SI use?

The AT28C64-12SI is packaged in a 28-lead Small Outline Integrated Circuit (SOIC) with 300-mil body width (package code "S"). It conforms to JEDEC MS-012 standards and features gull-wing surface-mount leads. This package is distinct from the PDIP ("P"), TSOP ("T"), or PLCC ("J") variants in the same family, and its pinout matches the JEDEC-standard 28-pin parallel EEPROM footprint, enabling mechanical and electrical compatibility with existing SOIC-based layouts.

Can the AT28C64-12SI be used in place of older 28C64 variants without design changes?

Yes-the AT28C64-12SI maintains full pin-to-pin and functional compatibility with earlier 28C64 versions (e.g., AT28C64-15, AT28C64-20) across all packages. Its JEDEC-approved byte-wide pinout, identical DC/AC specifications at rated speed, and shared command set (including Chip Clear and DATA polling) ensure drop-in replacement in legacy systems. No PCB, firmware, or timing modifications are required when upgrading from slower-speed variants, provided the 120 ns access time meets system timing margins.

What is the endurance rating and data retention specification for the AT28C64-12SI?

The AT28C64-12SI is rated for 10,000 write/erase cycles and guarantees 10 years of data retention at +85°C ambient temperature. These values are measured per JEDEC standards and apply across the full industrial temperature range. Endurance is defined as the number of guaranteed full-memory write cycles before parametric failure; retention reflects data integrity under worst-case thermal stress, making AT28C64-12SI appropriate for applications with infrequent but mission-critical updates such as calibration storage or configuration backup.