Microchip Technology AT28C64-12TC

Overview

AT28C64-12TC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 120 ns read access time, self-timed byte write (1 ms standard), CMOS/TTL-compatible I/O, and JEDEC-standard 28-pin TSOP package. It operates at 5V ±10%, supports commercial temperature range (0°C to 70°C), and delivers 30 mA active / 100 µA standby current for embedded microcontroller systems requiring nonvolatile configuration storage.

For engineers reviewing the AT28C64-12TC datasheet, AT28C64-12TC pinout, AT28C64-12TC application, or AT28C64-12TC equivalent, this page provides verified timing parameters, RDY/BUSY and DATA polling interface behavior, JEDEC-compliant pin mapping, endurance (10⁴ cycles), and real-world use cases in industrial control firmware and boot loader parameter retention.

Technical Context

The AT28C64-12TC implements a parallel EEPROM architecture with internal address/data latching and an autonomous control timer that manages erase-before-write sequencing without external timing components. Its READY/BUSY open-drain output and I/O7 data polling provide two hardware-synchronized methods to detect write completion.

It features VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, and triple-level write protection (CE/OE/WE logic gating). The device includes 32 bytes of dedicated identification EEPROM accessible via A9 = 12 V and addresses 1FE0H–1FFFH, and supports chip clear via 12 V on OE with WE pulse.

Key Specifications

Pinout & Package

AT28C64-12TC is housed in a 28-lead Plastic Thin Small Outline Package (TSOP), JEDEC MS-024 compliant, with 0.5 mm lead pitch and body dimensions 11.8 × 7.6 mm. Pin 1 is RDY/BUSY (open-drain) - functional in this variant per datasheet Rev. 0001H, Section "Pin Configurations".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64-12TC, AT28C64B-12TC offers enhanced data retention and tighter timing guarantees without layout changes, while MX28LV640CT-12G introduces voltage-level complexity but reduces active power consumption - making the original AT28C64-12TC optimal for cost-sensitive, 5 V-only legacy upgrades.

Availability

AT28C64-12TC is available at Aetrix Electronics and suitable for industrial control firmware storage, embedded boot loader configuration, and legacy instrumentation patch management requiring stable component supply across extended production lifecycles.

Supply support for AT28C64-12TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C64 series was designed as a pin-compatible, low-power upgrade path from EPROM and early EEPROM technologies for 8-bit microprocessor systems requiring reliable, byte-erasable nonvolatile storage.

FAQ

What is the maximum operating temperature range for the AT28C64-12TC?

The AT28C64-12TC is rated for commercial temperature operation from 0°C to +70°C. This specification is confirmed in the "DC and AC Operating Range" table on page 4 of the official Atmel datasheet (Rev. 0001H), where "AT28C64-12" is explicitly listed under the Commercial column. Industrial variants (e.g., AT28C64-12TI) extend to –40°C to +85°C, but the -TC suffix denotes the commercial-grade TSOP package.

Does the AT28C64-12TC support both RDY/BUSY and DATA polling for write completion detection?

Yes, the AT28C64-12TC supports both methods. Pin 1 functions as an open-drain RDY/BUSY output that goes low during write cycles and releases upon completion. Simultaneously, DATA polling is implemented by reading I/O7: it returns the complement of the written data until the write finishes, then outputs true data. Both mechanisms are fully documented in the "Device Operation" section (page 3) and confirmed for the AT28C64-12TC variant.

What is the endurance rating of the AT28C64-12TC, and how is it validated?

The AT28C64-12TC has an endurance rating of 10,000 write/erase cycles, as stated in the "Features" section (page 1) and "DC Characteristics" table (page 4). This value is derived from Atmel's qualification testing per JEDEC standards and applies specifically to the standard (non-E) version - the "E" suffix (e.g., AT28C64E) denotes 100,000-cycle endurance, which is not applicable to the AT28C64-12TC.

Can the AT28C64-12TC be used as a direct replacement for SRAM in existing designs?

Yes, the AT28C64-12TC can replace SRAM in read operations due to identical parallel interface timing and pinout, but write behavior differs fundamentally: it requires write enable assertion and supports only byte-level writes with self-timed duration (~1 ms). Unlike SRAM, it does not support simultaneous read/write or random write without explicit timing management - so bus arbitration logic must accommodate its asynchronous write completion signals (RDY/BUSY or DATA polling).

Is the 32-byte device identification area accessible on the AT28C64-12TC, and how is it enabled?

Yes, the AT28C64-12TC includes 32 bytes of user-accessible identification EEPROM at addresses 1FE0H–1FFFH. Access requires raising A9 to 12.0 V ± 0.5 V while applying standard CE/OE/WE control signals - a feature confirmed in the "DEVICE IDENTIFICATION" section (page 3) and applicable to all AT28C64 variants including the AT28C64-12TC. Standard 5 V operation is used for normal memory access.