Microchip Technology AT28C64-15SC
- Part No.:
- AT28C64-15SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28C64-15SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,552
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Product details
Overview
AT28C64-15SC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, 1 ms byte write cycle, and CMOS/TTL-compatible I/O. It operates at 5V ±10%, supports commercial temperature range (0°C to 70°C), and delivers 30 mA active current and 100 µA standby current for embedded microcontroller systems requiring nonvolatile configuration storage.
For engineers reviewing the AT28C64-15SC datasheet, AT28C64-15SC pinout, AT28C64-15SC application, or AT28C64-15SC equivalent, key selection criteria include its self-timed byte write, READY/BUSY or DATA polling completion detection, VCC-sense write protection, chip clear capability, and industrial-grade reliability (10⁴ write cycles, 10-year data retention).
Technical Context
The AT28C64-15SC functions as a drop-in SRAM-compatible nonvolatile memory: reads occur with CE and OE low and WE high; writes initiate on falling WE (or CE) edge with address and data latched internally. Its self-timed write cycle includes automatic erase-before-write and internal control timing-no external circuitry required.
Two hardware-level write completion detection methods are supported: open-drain RDY/BUSY output (pin 1, active-low during write) and DATA polling via I/O7 complement behavior. Write protection is enforced by VCC sensing (<3.8 V inhibits write), 5 ms power-on delay, and logic-level inhibit (OE high, CE high, or WE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); sufficient for firmware boot code, calibration tables, or device configuration in 8-bit microcontroller systems. |
| Read Access Time | 150 ns maximum; enables direct interfacing with 6–8 MHz Z80, 8051, or 68000-based systems without wait states. |
| Byte Write Time | 1 ms typical; self-timed cycle eliminates need for external timing control or busy-wait loops in host firmware. |
| Supply Voltage | 5V ±10%; compatible with legacy TTL/CMOS logic rails and avoids dedicated voltage regulation in cost-sensitive designs. |
| Endurance & Retention | 10,000 write/erase cycles minimum; 10-year data retention at 85°C-validated for field-deployed industrial controllers. |
| Operating Temperature | 0°C to 70°C; qualified for commercial-grade applications including point-of-sale terminals and office peripherals. |
| Standby Current | 100 µA maximum (CMOS mode); enables low-power sleep modes in battery-backed or energy-conscious systems. |
Pinout & Package
AT28C64-15SC is supplied in a 28-lead SOIC (Small Outline Integrated Circuit) package, 0.300" wide, JEDEC MS-012 compliant, with gull-wing leads and surface-mount footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; compatible with 8085, Z80, and 68000 upper address lines. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; electrically compatible with TTL/CMOS logic levels and directly connectable to microprocessor data buses. |
| CE | Chip Enable | Active-low chip select; enables memory access only when asserted-critical for multi-device bus arbitration. |
| OE | Output Enable | Active-low output control; allows high-impedance tri-state operation to prevent bus contention during shared-bus transfers. |
| WE | Write Enable | Active-low write strobe; initiates self-timed byte write on falling edge; also used for chip erase with A9 = 12 V. |
| RDY/BUSY | Open-Drain Status Output | Active-low signal indicating write progress; supports wired-OR connection across multiple EEPROMs on same status line. |
| VCC, GND | Power Supply | Single 5V supply with decoupling recommended; no separate VPP or programming voltage required for standard operation. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed byte write | Internal timer automates erase-and-program sequence-eliminates external timing circuitry and simplifies firmware integration. |
| Dual write completion detection | RDY/BUSY pin + DATA polling (I/O7 complement) provide flexible, hardware- or software-driven write synchronization options. |
| VCC-sense write protection | Hardware lockout below 3.8 V prevents accidental writes during power ramp-up or brownout conditions. |
| Chip Clear function | Entire memory set to FFh via 12 V on A9 and 10 ms WE pulse-enables factory reset or secure initialization without full reprogramming. |
| User-accessible ID area | 32 bytes at 1FE0H–1FFFH allow serialization, calibration data, or firmware version storage independent of main array. |
Applications
| Industrial PLC Configuration Storage | Embedded Printer Firmware Bootloader |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up and runtime parameter updates; requires guaranteed 10⁴ endurance and 10-year data retention at 70°C ambient. Use Value: Eliminates need for battery-backed SRAM; supports field updates via serial interface without external high-voltage programming circuitry. | Use Scenario: Holding printer firmware boot code and font data in thermal label printers operating in retail and warehouse settings. IC Role / Device Role / Timing Role: Parallel-boot memory mapped to microcontroller address space; read access must meet 150 ns timing to avoid CPU wait states during cold start. Use Value: Enables zero-footprint firmware upgrades via host PC-byte-write capability allows patching individual routines without full chip erase. |
| Point-of-Sale Terminal Settings | Medical Device Calibration Data |
Use Scenario: Persisting tax rate tables, receipt formatting rules, and user preferences in POS terminals subject to frequent power cycling. IC Role / Device Role / Timing Role: Low-power configuration store; standby current ≤100 µA extends backup battery life during AC outage. Use Value: VCC-sense protection prevents corruption during unstable mains conditions; JEDEC pinout ensures compatibility with legacy board layouts. | Use Scenario: Recording sensor calibration coefficients and usage logs in portable diagnostic equipment certified to IEC 60601-1. IC Role / Device Role / Timing Role: Tamper-resistant nonvolatile storage; chip clear function enables secure data wipe before device decommissioning. Use Value: 32-byte ID area stores unique device serial number and calibration timestamp-traceable per regulatory requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-15SC | Enhanced revision with improved data retention (20 years), tighter tACC spec (150 ns guaranteed), and extended VCC tolerance (4.5–5.5 V). | Preferred for new designs requiring longer lifetime or wider supply margin; pinout and timing otherwise identical. | Select AT28C64B-15SC for production builds where long-term reliability and supply stability are critical. |
| MX28LV640CT-15G | 3.3 V core with 5 V tolerant I/O; 150 ns access; 100K endurance; TSOP-32 package (not pin-compatible). | Requires level-shifting or redesign for 5 V-only systems; better suited for mixed-voltage or low-power portable applications. | Choose MX28LV640CT-15G only when migrating to 3.3 V architecture or needing higher endurance-board layout change required. |
Compared with AT28C64-15SC, AT28C64B-15SC offers verified longevity and tighter specs without layout impact, while MX28LV640CT-15G demands voltage and footprint changes but delivers 10× endurance-making it suitable only for next-generation 3.3 V designs.
Availability
AT28C64-15SC is available at Aetrix Electronics and suitable for industrial control systems, embedded printers, point-of-sale terminals, and medical instrumentation requiring stable component supply across extended product lifecycles.
Supply support for AT28C64-15SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) designed high-reliability nonvolatile memory and microcontroller solutions for industrial, automotive, and consumer applications.
The AT28C64 family was engineered as a plug-compatible EEPROM replacement for EPROM and battery-backed SRAM in legacy 8-bit systems-prioritizing ease of migration, robust write protection, and JEDEC-standard packaging.
FAQ
What is the maximum read access time specified for the AT28C64-15SC?
The AT28C64-15SC has a maximum read access time (tACC) of 150 ns under commercial temperature conditions (0°C to 70°C) and 5V ±10% supply. This value is guaranteed across all operating conditions specified in the datasheet and enables direct interface with microprocessors such as the 8051 or Z80 without wait-state insertion.
Does the AT28C64-15SC require an external high-voltage supply for normal write operations?
No, the AT28C64-15SC does not require external high voltage for standard byte writes. All write operations-including self-timed byte programming and DATA polling-use only the standard 5V supply. A 12 V pulse on A9 is needed only for the optional Chip Clear function, not routine writes.
How does write protection work on the AT28C64-15SC?
The AT28C64-15SC implements three-tiered hardware write protection: (1) VCC sense disables writes if supply drops below ~3.8 V; (2) a 5 ms internal delay after power-on before writes are enabled; and (3) logical inhibition-holding OE high, CE high, or WE high blocks all write cycles. These features prevent accidental overwrites during power transitions or firmware errors.
Can the AT28C64-15SC be used as a direct replacement for standard SRAM in existing designs?
Yes-the AT28C64-15SC uses JEDEC-standard byte-wide pinout and behaves like SRAM during reads and writes: CE/OE/WE control signals match standard memory interface timing, and no external timing components are needed. However, write cycles take 1 ms (vs. nanosecond SRAM writes), so firmware must accommodate completion detection via RDY/BUSY or DATA polling.
What package type is used for the AT28C64-15SC, and what are its key mechanical features?
The AT28C64-15SC is packaged in a 28-lead SOIC (Small Outline IC), 0.300" wide, with gull-wing leads. It conforms to JEDEC MS-012, has a body size of 17.9 × 7.6 mm, and is optimized for surface-mount reflow assembly. Pin 1 is marked by a beveled corner, and the package supports standard PCB footprints used for 28-pin memory devices.
AT28C64-15SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 150 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28C64-15SC FAQ
1.How can I place an order for AT28C64-15SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64-15SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64-15SC reliable?
The price and inventory of AT28C64-15SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64-15SC is usually 5 days.
3.What payment methods are accepted for AT28C64-15SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64-15SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64-15SC?
AT28C64-15SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64-15SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64-15SC?
For technical support, including AT28C64-15SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64-15SC requirements.
6.How does Aetrix verify that AT28C64-15SC is sourced from the original manufacturer or authorized distributors?
All AT28C64-15SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64-15SC meets industry standards.
7.What is the process for return or replacement of AT28C64-15SC?
All AT28C64-15SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64-15SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64-15SC part is unused and in its original packaging.
Return procedure for AT28C64-15SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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