Microchip Technology AT28C64-20JC

Overview

AT28C64-20JC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 1 ms fast byte write cycle, and CMOS/TTL-compatible I/O for direct microprocessor interfacing in embedded control systems.

For engineers reviewing the AT28C64-20JC datasheet, AT28C64-20JC pinout, AT28C64-20JC application, or AT28C64-20JC equivalent, this device supports reliable nonvolatile storage in industrial PLCs, legacy BIOS modules, and field-programmable configuration memory where self-timed writes, RDY/BUSY signaling, and 5V ±10% operation are required.

Technical Context

The AT28C64-20JC operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on falling WE (or CE) edge with internal latching of address and data, followed by autonomous clear-and-write using an integrated timer. It supports two end-of-write detection methods: open-drain RDY/BUSY output and DATA polling on I/O7.

Its architecture includes VCC-sense write protection (inhibits below 3.8 V), 5 ms power-on delay before write enable, and chip erase via 12 V on OE. The device also provides 32 bytes of user-accessible identification EEPROM at addresses 1FE0H–1FFFH using A9 = 12 V.

Key Specifications

Pinout & Package

AT28C64-20JC is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), JEDEC MS-016 AE compliant, with pin 1 indexed and pins 1 and 17 marked "DON'T CONNECT" per datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64-20JC, the AT28C64B-20JC offers superior long-term reliability and lower power, while the MX28F640KC-20JC trades autonomous write timing for broader ecosystem compatibility-making the original AT28C64-20JC optimal for simplicity and self-contained operation in resource-constrained designs.

Availability

AT28C64-20JC is available at Aetrix Electronics and suitable for industrial PLCs, legacy BIOS modules, and embedded instrumentation requiring stable component supply, long-lifecycle support, and proven 5 V parallel EEPROM functionality.

Supply support for AT28C64-20JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation was a U.S.-based semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs, acquired by Microchip Technology in 2016.

The AT28C64 family was designed as a pin-compatible, SRAM-drop-in replacement EEPROM for industrial and computing applications requiring field-upgradable nonvolatile storage without external timing or high-voltage programming circuitry.

FAQ

What is the maximum read access time specified for AT28C64-20JC?

The AT28C64-20JC has a maximum read access time of 200 ns, measured from address stabilization to valid data on I/O0–I/O7 under commercial temperature range (0°C to 70°C) and 5 V ±10% supply. This value is guaranteed per the AC Read Characteristics table and applies specifically to the -20 speed grade, distinguishing it from slower -25 (250 ns) or faster -12 (120 ns) variants.

Does AT28C64-20JC support both RDY/BUSY signaling and DATA polling?

Yes, AT28C64-20JC supports both RDY/BUSY signaling via its open-drain Pin 1 and DATA polling on I/O7. During a write cycle, reading the target location returns the complement of the written data on I/O7 until completion, at which point true data appears. RDY/BUSY is actively pulled low during write and released high afterward, enabling hardware handshaking.

What package type is used for AT28C64-20JC?

AT28C64-20JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package, designated as 32J per Atmel's ordering information. Pins 1 and 17 are explicitly marked "DON'T CONNECT" in the datasheet, and the package complies with JEDEC standard MS-016 AE.

Can AT28C64-20JC be used as a direct replacement for standard SRAM in existing designs?

AT28C64-20JC is designed for SRAM-like read/write access without external components, but it is not a direct SRAM replacement due to its 1 ms write cycle and required write-protection logic. Reads mirror SRAM behavior (CE/OE low, WE high), but writes require proper timing and status monitoring-making it suitable for non-critical, infrequent storage rather than high-speed RAM emulation.

What is the endurance rating and data retention specification for AT28C64-20JC?

AT28C64-20JC is rated for 10,000 write/erase cycles and guarantees 10 years of data retention at 85°C. These values are confirmed in the "High Reliability" section and DC/AC specifications, and apply to the standard (non-E) variant indicated by the absence of "E" suffix in the part number.