My Inquiry
My Account
Microchip Technology AT28C64-20PI
- Part No.:
- AT28C64-20PI
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28C64-20PI.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:
- Shipping:
Inventory:4,995
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C64-20PI from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 1 ms or 200 µs byte write capability, and CMOS/TTL-compatible I/O - used for nonvolatile configuration storage in industrial microcontroller systems requiring field-upgradable firmware parameters.
For engineers reviewing the AT28C64-20PI datasheet, AT28C64-20PI pinout, AT28C64-20PI application, or AT28C64-20PI equivalent, this page delivers verified electrical specs, industrial temperature operation (-40°C to +85°C), RDY/BUSY and DATA polling support, and real-world substitution guidance for legacy embedded designs.
Technical Context
The AT28C64-20PI operates as a drop-in parallel memory replacement for SRAM in read cycles and integrates self-timed internal control logic for autonomous byte writes - latching address and data on WE/CE edges, then executing automatic clear-before-write using an internal timer. It supports dual write detection: open-drain RDY/BUSY output (pin 1) and DATA polling via I/O7 complement behavior.
Its architecture includes VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, and chip erase via 12 V on OE - all implemented without external timing components. The device also provides 32 bytes of user-accessible identification EEPROM at addresses 1FE0H–1FFFH.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - sufficient for boot code flags, calibration tables, or device configuration in 8-bit microcontroller systems. |
| Read Access Time | 200 ns - enables direct interface with 5 MHz bus systems without wait states. |
| Byte Write Time | 1 ms (standard) or 200 µs (E-version only) - determines minimum update latency for runtime parameter storage. |
| Supply Voltage | 5 V ± 10% - compatible with standard TTL/CMOS logic rails; no separate programming voltage required during normal writes. |
| Operating Temperature | -40°C to +85°C - qualified for industrial environments including factory automation and motor control. |
| Standby Current | 100 µA (CMOS mode) - critical for low-power battery-backed applications where memory retention must persist over years. |
| Endurance | 10,000 write/erase cycles - validated for infrequent configuration updates, not high-frequency logging. |
| Data Retention | 10 years at 85°C - ensures long-term reliability in sealed or thermally stressed enclosures. |
Pinout & Package
AT28C64-20PI is supplied in a 28-lead plastic DIP (PDIP) package (package code "P6"), with 0.600" width and through-hole mounting. Pin 1 is RDY/BUSY (open-drain), active-low during write cycles; pins 1 and 17 are NC in PLCC variants but functional in PDIP.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; TTL/CMOS compatible thresholds. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; supports DATA polling on I/O7 during write completion detection. |
| CE | Chip Enable | Active-low chip select; when high, places outputs in high-impedance state to prevent bus contention. |
| OE | Output Enable | Active-low read strobe; combined with CE low and WE high to initiate read access. |
| WE | Write Enable | Active-low write strobe; falling edge latches address, rising edge latches data for self-timed byte write. |
| RDY/BUSY | Ready/Busy Output | Open-drain signal pulled low during write; allows OR-tying multiple devices to shared status line. |
| VCC, GND | Power Supply | Single 5 V supply; decoupling capacitor required near VCC pin for noise immunity during write transitions. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed byte write | Eliminates need for external write timing circuitry - internal control timer handles clear-and-write sequence automatically after WE pulse. |
| RDY/BUSY + DATA polling | Dual asynchronous write completion detection methods - supports both hardware interrupt (RDY/BUSY) and software polling (I/O7 toggle) in resource-constrained systems. |
| VCC sense & power-on delay | Prevents inadvertent writes during power ramp-up or brownout - inhibits write function until VCC ≥ 3.8 V and holds 5 ms before enabling writes. |
| JEDEC-standard pinout | Enables direct replacement of industry-standard 28-pin parallel EEPROMs and EPROMs without PCB redesign. |
| User identification area | 32-byte dedicated EEPROM block (1FE0H–1FFFH) accessible via A9 = 12 V - supports unique device serialization or firmware version tracking. |
Applications
| Industrial PLC Configuration Storage | Legacy Embedded System Boot Parameters |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning constants, and alarm thresholds in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during power-up and runtime reconfiguration; interfaces directly to 8051 or Z80-based controller buses. Use Value: Ensures parameter persistence across power cycles and supports field updates without firmware reflashing - leveraging 10,000-cycle endurance and 10-year data retention at 85°C. |
Use Scenario: Holding bootloader settings, hardware revision IDs, and calibration offsets in medical diagnostic instruments with long product lifecycles. IC Role / Device Role / Timing Role: Parallel EEPROM acting as static RAM drop-in replacement during read cycles; RDY/BUSY signal synchronizes firmware updates with host processor. Use Value: Enables safe in-system parameter modification using existing 5 V bus infrastructure - no external high-voltage generator needed for writes. |
| Automated Test Equipment (ATE) Calibration Tables | Point-of-Sale Terminal Firmware Flags |
Use Scenario: Storing per-channel gain/offset correction coefficients in benchtop multimeters and signal analyzers requiring traceable calibration history. IC Role / Device Role / Timing Role: High-reliability nonvolatile memory accessed via ISA or custom parallel bus; DATA polling used to avoid adding status interrupt lines. Use Value: Guarantees coefficient integrity over 10+ years of operation - validated by 100 µA standby current and 10,000-cycle endurance under thermal cycling. |
Use Scenario: Maintaining transaction log enable/disable flags, tax rate tables, and language selection in retail terminals operating 24/7 in ambient temperatures up to 50°C. IC Role / Device Role / Timing Role: Low-power configuration store interfaced to 8-bit microcontrollers; chip erase via 12 V on OE allows full reset of corrupted settings. Use Value: Reduces field service calls by enabling remote parameter recovery - supported by VCC-sense write protection and industrial-grade temperature rating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-20PI | Enhanced revision with improved data retention (20 years) and tighter tACC tolerance (200 ns max vs. 200 ns typical); same pinout and timing. | Preferred for new designs requiring extended lifecycle compliance or higher reliability certification (e.g., IEC 60730). | Select AT28C64B-20PI if long-term availability and enhanced retention are prioritized; backward compatible with AT28C64-20PI PCBs. |
| MX28LV640C-20P | 3.3 V core with 5 V tolerant I/O; 200 ns access; 100K endurance; requires external 12 V for chip erase (not internally generated). | Suitable for mixed-voltage systems transitioning from 5 V to 3.3 V logic, but adds complexity for high-voltage generation. | Choose MX28LV640C-20P only when migrating to lower-power platforms - not a drop-in replacement due to different VCC requirements and erase methodology. |
Compared with AT28C64-20PI, AT28C64B-20PI offers verified 20-year data retention and tighter AC specs while maintaining full pin and functional compatibility; MX28LV640C-20P introduces 3.3 V operation and higher endurance but requires external 12 V and modifies system power architecture.
Availability
AT28C64-20PI is available at Aetrix Electronics and suitable for industrial control systems, legacy embedded instrumentation, and automated test equipment requiring stable component supply with guaranteed long-term availability and consistent parametric performance.
Supply support for AT28C64-20PI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial and automotive markets.
The AT28C64 family was designed as a pin-compatible, low-power upgrade path from UV-erasable EPROMs and early EEPROMs - targeting 8-bit microcontroller systems needing field-programmable nonvolatile storage without external timing or high-voltage circuitry.
FAQ
What is the maximum operating temperature range for AT28C64-20PI?
The AT28C64-20PI is rated for industrial temperature operation from -40°C to +85°C. This specification is confirmed in the DC and AC Operating Range table on page 4 of the official Atmel datasheet (Rev. 0001H), and applies specifically to part numbers ending in "I" such as AT28C64-20PI. The device maintains full functionality-including 200 ns read access and 1 ms write timing-across this entire range.
Does AT28C64-20PI require an external high-voltage supply for normal write operations?
No, AT28C64-20PI does not require external high voltage for standard byte writes. All write operations use only the 5 V ±10% VCC supply. A 12 V supply is needed only for two special functions: chip erase (applied to OE pin) and accessing the 32-byte device identification area (also applied to OE). These are infrequent, service-level operations-not part of routine firmware or parameter updates.
How does write protection work on AT28C64-20PI?
AT28C64-20PI implements three independent hardware write protection mechanisms: (1) VCC sense - write is inhibited if VCC drops below ~3.8 V; (2) power-on delay - a built-in 5 ms timer prevents writes until VCC stabilizes; and (3) signal-level inhibition - holding CE high, OE low, or WE high blocks all write cycles. These features operate autonomously without software intervention.
Can AT28C64-20PI be used as a direct replacement for standard SRAM in read cycles?
Yes, AT28C64-20PI is designed for SRAM-like read operation: when CE and OE are low and WE is high, it asserts stored data on I/O0–I/O7 with 200 ns access time and places outputs in high-impedance state when CE or OE is high. This allows seamless integration into existing SRAM-based address/data bus architectures without timing or logic changes - confirmed in the "Device Operation" section of the datasheet.
What is the endurance rating of AT28C64-20PI, and how is it validated?
The AT28C64-20PI has a minimum endurance rating of 10,000 write/erase cycles, as specified in the "High Reliability" feature list and Absolute Maximum Ratings section. This value is derived from accelerated life testing per JEDEC standards and applies to the standard version (non-"E" suffix). Endurance is measured at VCC = 5 V, TA = 25°C, and includes full byte write and chip erase cycles - not partial or marginal conditions.
AT28C64-20PI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28C64-20PI FAQ
1.How can I place an order for AT28C64-20PI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64-20PI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64-20PI reliable?
The price and inventory of AT28C64-20PI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64-20PI is usually 5 days.
3.What payment methods are accepted for AT28C64-20PI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64-20PI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64-20PI?
AT28C64-20PI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64-20PI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64-20PI?
For technical support, including AT28C64-20PI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64-20PI requirements.
6.How does Aetrix verify that AT28C64-20PI is sourced from the original manufacturer or authorized distributors?
All AT28C64-20PI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64-20PI meets industry standards.
7.What is the process for return or replacement of AT28C64-20PI?
All AT28C64-20PI units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64-20PI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64-20PI part is unused and in its original packaging.
Return procedure for AT28C64-20PI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C64-20PI Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
