My Inquiry
My Account
Microchip Technology AT28C64-20SC
- Part No.:
- AT28C64-20SC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT28C64-20SC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,274
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C64-20SC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 1 ms or 200 µs byte write capability, and CMOS/TTL-compatible I/O-used for nonvolatile configuration storage in industrial microcontroller systems requiring field-upgradable firmware parameters.
For engineers reviewing the AT28C64-20SC datasheet, AT28C64-20SC pinout, AT28C64-20SC application, or AT28C64-20SC equivalent, key selection considerations include its self-timed write cycle, READY/BUSY open-drain output, DATA polling support, 5V ±10% supply operation, and industrial temperature range (-40°C to +85°C) in SOIC package.
Technical Context
The AT28C64-20SC operates as a drop-in parallel memory replacement for SRAM in read cycles and implements internal address/data latching during byte writes. Its self-timed write cycle includes automatic clear-before-write and internal control timing-eliminating external wait-state logic.
It supports two hardware-based write completion detection methods: level-sensitive RDY/BUSY (open-drain, pin 1) and DATA polling on I/O7. Write protection is enforced via VCC sense (<3.8 V inhibits write), power-on delay (~5 ms), and signal-level inhibition (OE high, CE high, or WE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); provides sufficient space for boot code flags, calibration tables, or device ID storage in embedded controllers. |
| Read Access Time | 200 ns max; enables direct interfacing with 5 MHz bus systems without wait states. |
| Byte Write Time | 1 ms standard (or 200 µs for E-version); determines minimum time between successive byte updates in parameter logging applications. |
| Supply Voltage | 5 V ±10%; compatible with legacy 5 V microcontroller buses and eliminates need for level-shifting circuitry. |
| Operating Temperature | -40°C to +85°C; qualified for industrial environments including factory automation and motor control systems. |
| Standby Current | 100 µA typical; reduces system power budget during sleep modes in battery-backed or energy-conscious designs. |
| Endurance | 10,000 write/erase cycles; supports infrequent but critical field updates such as firmware revision tracking or calibration offset storage. |
| Data Retention | 10 years at 85°C; ensures long-term reliability of stored configuration data without refresh. |
Pinout & Package
AT28C64-20SC is packaged in a 28-lead, 0.300" wide plastic SOIC (Small Outline Integrated Circuit) per JEDEC MS-012, with gull-wing leads and surface-mount compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; directly driven by MCU address lines A0–A12. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface; shares pins for read output and write input-requires no separate data direction control. |
| CE | Chip Enable | Active-low chip select; enables memory access only when asserted-prevents bus contention during peripheral arbitration. |
| OE | Output Enable | Active-low read strobe; places outputs in high-impedance state when deasserted, enabling shared bus operation. |
| WE | Write Enable | Active-low write strobe; initiates self-timed byte write on falling edge; latches address and data internally. |
| RDY/BUSY | Ready/Busy Output | Open-drain status signal pulled low during write; allows OR-tying with other devices for centralized busy monitoring. |
| VCC | Power Supply | +5 V ±10% supply; powers core logic and memory array; decoupling capacitor required near pin. |
| GND | Ground Reference | Signal and power return path; must be low-impedance connection to minimize noise coupling into data lines. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Byte Write | Eliminates external timing circuitry-internal control timer manages erase-and-program sequence automatically after WE assertion. |
| DATA Polling Support | Enables software-driven write completion detection via I/O7 complement behavior-no dedicated status pin required. |
| RDY/BUSY Open-Drain Output | Allows multiple AT28C64-20SC devices to share a single BUSY line using wired-OR logic-reduces GPIO count in multi-EEPROM systems. |
| VCC Sense Write Inhibit | Prevents corruption during brown-out conditions by disabling writes if VCC drops below ~3.8 V-ensures data integrity during power transitions. |
| JEDEC Byte-Wide Pinout | Guarantees compatibility with existing PCB layouts designed for industry-standard 28-pin parallel EEPROMs-enables drop-in replacement. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory-floor environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing persistent parameter storage accessible via parallel bus during boot and runtime reconfiguration. Use Value: Enables field updates without firmware reflashing; 10K endurance and 10-year retention ensure reliability across maintenance cycles. | Use Scenario: Holding sensor calibration coefficients, patient-specific therapy settings, and device serialization data in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, low-power parameter memory accessed during startup and service mode-immune to power loss during clinical use. Use Value: 100 µA standby current extends battery life; industrial temp rating supports operation in sterilized or temperature-variable enclosures. |
| Automotive Body Control Module | Test Equipment Setup Profiles |
Use Scenario: Saving user preferences, door lock programming, and lighting configuration in automotive BCMs operating under engine-bay thermal stress. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to 8-bit MCU-provides deterministic 200 ns read latency for real-time response to CAN-triggered events. Use Value: -40°C to +85°C rating meets AEC-Q100 ambient requirements; VCC sense prevents write corruption during cranking voltage dips. | Use Scenario: Storing instrument calibration offsets, test sequence definitions, and operator permissions in automated benchtop test systems. IC Role / Device Role / Timing Role: Field-upgradable memory for test firmware metadata-accessed during initialization and maintenance mode via dedicated test port. Use Value: Chip Clear function (12 V on OE) enables secure factory reset; 32-byte ID area supports traceability and version control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-20SC | Enhanced revision with improved data retention (20 years) and tighter DC specs; same pinout, timing, and command set. | Preferred for new designs requiring extended lifecycle data integrity-especially in medical or aerospace applications. | Select AT28C64B-20SC when long-term archival reliability is prioritized over cost-sensitive legacy compatibility. |
| MX28LV640CT-20G | 64 Mbit capacity, 3.3 V core (with 5 V tolerant I/O), 200 ns access; requires level translation for pure 5 V systems. | Suitable for higher-density storage needs where board space permits SOIC-28 footprint and voltage translation is acceptable. | Choose MX28LV640CT-20G only if migrating to 3.3 V infrastructure or requiring >64 Kbit capacity-otherwise not a direct substitute. |
Compared with AT28C64-20SC, the AT28C64B-20SC offers superior data retention without layout or firmware changes, while MX28LV640CT-20G introduces voltage and density trade-offs that require system-level redesign-not just component substitution.
Availability
AT28C64-20SC is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and automated test equipment requiring stable component supply across extended production lifecycles.
Supply support for AT28C64-20SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and security ICs for embedded applications.
The AT28C64 product line was designed as a pin-compatible, low-power parallel EEPROM family targeting legacy 5 V microprocessor systems needing reliable, field-updatable configuration storage without external timing components.
FAQ
What is the maximum read access time specified for the AT28C64-20SC?
The AT28C64-20SC has a maximum read access time of 200 ns, measured from address valid to valid data output under commercial and industrial temperature ranges with VCC = 5 V ±10%. This value is guaranteed per the AC Read Characteristics table in the official Atmel datasheet Rev. 0001H–12/99 and applies specifically to the -20 speed grade variant of the AT28C64-20SC.
Does the AT28C64-20SC support both hardware and software write completion detection?
Yes, the AT28C64-20SC supports dual write completion detection: hardware-based RDY/BUSY signaling via an open-drain output (pin 1), and software-based DATA polling by monitoring the complement state of I/O7 during write cycles. Both methods are fully functional in the AT28C64-20SC and documented in the Device Operation section of the datasheet.
What package type and lead count does the AT28C64-20SC use?
The AT28C64-20SC uses a 28-lead, 0.300" wide plastic SOIC (Small Outline Integrated Circuit) package, also referred to as 28S in Atmel's ordering nomenclature. This surface-mount package conforms to JEDEC MS-012 standards and is distinct from PDIP, TSOP, or PLCC variants offered in the same AT28C64 family.
Can the AT28C64-20SC be used in 3.3 V systems?
No-the AT28C64-20SC is strictly a 5 V ±10% device and is not rated for 3.3 V operation. Its DC characteristics, including input thresholds (VIL = 0.8 V, VIH = 2.0 V), output drive strength, and internal charge pump operation assume a 5 V supply. Using it with 3.3 V may result in unreliable reads, failed writes, or premature wear.
Is the AT28C64-20SC pin-compatible with the AT28C64B-20SC?
Yes-the AT28C64-20SC is fully pin-compatible and functionally interchangeable with the AT28C64B-20SC. The B-version is a second-source enhanced revision with identical pinout, timing, and command set, but improved data retention (20 years vs. 10 years) and tighter DC specifications. No PCB or firmware changes are required for substitution.
AT28C64-20SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SOIC
AT28C64-20SC FAQ
1.How can I place an order for AT28C64-20SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64-20SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64-20SC reliable?
The price and inventory of AT28C64-20SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64-20SC is usually 5 days.
3.What payment methods are accepted for AT28C64-20SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64-20SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64-20SC?
AT28C64-20SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64-20SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64-20SC?
For technical support, including AT28C64-20SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64-20SC requirements.
6.How does Aetrix verify that AT28C64-20SC is sourced from the original manufacturer or authorized distributors?
All AT28C64-20SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64-20SC meets industry standards.
7.What is the process for return or replacement of AT28C64-20SC?
All AT28C64-20SC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64-20SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64-20SC part is unused and in its original packaging.
Return procedure for AT28C64-20SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C64-20SC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
