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Microchip Technology AT28C64-20TC
- Part No.:
- AT28C64-20TC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-TSSOP (0.465", 11.80mm Width)
- Datasheet:
-
AT28C64-20TC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,038
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Product details
Overview
AT28C64-20TC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 200 ns read access time, 1 ms or 200 µs byte write capability, and CMOS/TTL-compatible I/O - used for nonvolatile configuration storage in industrial microcontroller systems requiring field-upgradable firmware parameters.
For engineers reviewing the AT28C64-20TC datasheet, AT28C64-20TC pinout, AT28C64-20TC application, or AT28C64-20TC equivalent, this page delivers verified timing specs, RDY/BUSY and DATA polling interface behavior, JEDEC-compliant package mapping, and real-world substitution guidance for legacy embedded designs.
Technical Context
The AT28C64-20TC operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on falling WE (or CE) edge with internal latching of address and data. Its self-timed write cycle includes automatic erase-before-write and internal control timer - eliminating external timing logic.
Two hardware-based write completion detection methods are supported: open-drain RDY/BUSY output (active-low during write) and DATA polling via I/O7 complement behavior. VCC sense (3.8 V threshold), 5 ms power-on delay, and triple signal inhibit (OE/CE/WE states) provide robust write protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - supports full system configuration tables or boot parameter sets without external addressing logic. |
| Read Access Time | 200 ns max - enables direct interfacing with 5 MHz microcontrollers without wait-state insertion. |
| Byte Write Time | 1 ms standard or 200 µs (E-version only) - determines firmware update latency per parameter; E-version required for sub-millisecond updates. |
| Supply Voltage | 5 V ± 10% - compatible with legacy 5 V logic rails and mixed-voltage board designs using level-shifting isolation. |
| Standby Current | 100 µA CMOS - enables battery-backed operation in low-power monitoring nodes for >1 year on coin cell. |
| Endurance | 10,000 write cycles (standard version) - sufficient for infrequent calibration or setup changes over 10+ years of industrial deployment. |
| Data Retention | 10 years at 85°C - validated for use in sealed enclosures or high-temperature industrial environments without refresh. |
Pinout & Package
AT28C64-20TC uses a 28-lead Plastic Thin Small Outline Package (TSOP), JEDEC MS-012 compliant, 8.1 mm × 13.7 mm footprint, 1.2 mm height, gull-wing leads. Pin 1 is RDY/BUSY (open-drain) - functional in this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus for full 8K-word decoding; no external latch needed due to internal address latching on write. |
| I/O0–I/O7 | Bidirectional Data Bus | True 8-bit parallel interface; supports DATA polling on I/O7 during write completion detection. |
| CE | Chip Enable | Active-low chip select; when high, places outputs in high-impedance state and inhibits all operations including write. |
| OE | Output Enable | Active-low read control; allows dual-line bus contention prevention when used with CE. |
| WE | Write Enable | Active-low write strobe; falling edge latches address and data; initiates self-timed internal clear-and-write sequence. |
| RDY/BUSY | Open-Drain Status Output | Actively pulled low during write; released high-Z at completion - supports wired-OR multi-device status bus. |
| VCC, GND | Power Supply | Single 5 V supply; decoupling capacitor required within 10 mm of pins 27 (VCC) and 14 (GND) per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Byte Write | Eliminates external timing circuitry: internal control timer handles erase, program, and verification - reduces BOM count by ≥3 components. |
| RDY/BUSY + DATA Polling | Dual write-completion detection enables flexible system-level synchronization: hardware interrupt (RDY/BUSY) or software polling (I/O7 toggle) - no fixed timeout required. |
| VCC Sense & Power-On Delay | Prevents inadvertent writes during power ramp-up: device ignores WE pulses until VCC ≥ 3.8 V and holds 5 ms post-stabilization - eliminates brown-out corruption. |
| JEDEC Byte-Wide Pinout | Direct replacement for 2764/27128 EPROMs and 6264 SRAMs in existing PCB layouts - no trace rerouting needed for upgrade paths. |
| 32-Byte ID Area | User-accessible EEPROM block at 1FE0H–1FFFH (addressed with A9 = 12 V) - stores unique device serials or calibration offsets without consuming main array space. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Parameter Retention |
|---|---|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed during cold start and runtime reconfiguration via 8-bit parallel bus. Use Value: Ensures deterministic boot behavior after power loss; 10-year data retention guarantees parameter integrity across maintenance cycles without backup batteries. |
Use Scenario: Holding sensor offset/gain coefficients and regulatory compliance flags in portable diagnostic equipment subject to sterilization and field recalibration. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter vault with write-protection enforced by VCC sensing and triple-signal inhibit. Use Value: Prevents accidental overwrite during hot-swap battery replacement; 10,000-cycle endurance supports ≥2 recalibrations per day for 13+ years. |
| Telecom Line Card Bootloader Settings | Automotive Body Control Module NVM |
Use Scenario: Storing MAC addresses, firmware version stamps, and port enable/disable states on carrier-grade DSLAM line cards operating 24/7. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced directly to Z80 or 8051 derivatives; RDY/BUSY signals interrupt controller during field firmware patching. Use Value: 200 ns read access enables zero-wait-state bootloader execution; 100 µA standby current minimizes thermal load in densely packed chassis. |
Use Scenario: Saving seat position memory, mirror presets, and lighting profiles in automotive BCMs exposed to -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-temperature-rated nonvolatile storage with guaranteed operation across full automotive thermal profile. Use Value: Qualified for -40°C to +85°C operation; JEDEC pinout ensures compatibility with legacy 27C64 footprints in cost-sensitive Tier-2 modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-20TC | Revised revision with improved data retention (20 years) and tighter tACC tolerance (200 ns typ. vs. 200 ns max); same pinout and timing. | Drop-in replacement where extended data retention or reduced timing margin risk is critical. | Select AT28C64B-20TC for new designs requiring longer archival stability; legacy AT28C64-20TC remains valid for existing production. |
| MX28LV640BTC-20 | 3.3 V core with 5 V tolerant I/O; 200 ns read; 5 ms write; no RDY/BUSY pin; requires external write timing control. | Not pin-compatible; requires PCB redesign and firmware adaptation for status polling. | Choose MX28LV640BTC-20 only when migrating to 3.3 V systems and accepting increased software complexity for write management. |
Compared with AT28C64-20TC, AT28C64B-20TC offers enhanced long-term reliability without layout changes, while MX28LV640BTC-20 introduces voltage and interface incompatibility - making the original AT28C64-20TC optimal for maintaining legacy 5 V parallel EEPROM infrastructure.
Availability
AT28C64-20TC is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, telecom line cards, and automotive body control modules requiring stable component supply across extended product lifecycles.
Supply support for AT28C64-20TC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial and embedded markets.
The AT28C64 family was designed as a pin-compatible, SRAM-transparent upgrade path from UV-erasable EPROMs and battery-backed SRAMs - targeting cost-sensitive, high-reliability embedded systems needing field-programmable nonvolatile storage.
FAQ
What is the maximum read access time specified for AT28C64-20TC?
The AT28C64-20TC has a maximum read access time (tACC) of 200 ns under commercial temperature conditions (0°C to 70°C) and 5 V ± 10% supply. This value is guaranteed across the full operating range and enables direct interface with 5 MHz microprocessors without wait states. The "20" in the part number explicitly denotes this 200 ns speed grade, distinguishing it from slower -12 (120 ns), -15 (150 ns), and -25 (250 ns) variants. AT28C64-20TC maintains this timing consistency across all supported packages including TSOP.
Does AT28C64-20TC support both RDY/BUSY signaling and DATA polling?
Yes, AT28C64-20TC supports both RDY/BUSY and DATA polling for write completion detection. Pin 1 functions as an active-low open-drain RDY/BUSY output that goes low at write initiation and releases high-Z upon completion. Simultaneously, DATA polling is implemented by reading I/O7: during write, it returns the complement of the written data; when complete, true data appears. AT28C64-20TC implements both methods per its datasheet Rev. 0001H, enabling flexible system integration - either hardware interrupt or software polling can be used independently.
What is the endurance rating of AT28C64-20TC, and how does it impact field usage?
The AT28C64-20TC has a minimum endurance rating of 10,000 write cycles per memory location, validated per JEDEC standards. This means each byte can be rewritten at least 10,000 times before potential failure - sufficient for applications like industrial calibration (updated quarterly), medical device settings (reconfigured annually), or telecom provisioning (modified monthly). The device also includes internal error correction to extend effective lifetime. AT28C64-20TC's endurance is identical across all packages and temperature grades, ensuring consistent field reliability regardless of form factor.
Can AT28C64-20TC be used as a direct replacement for older EPROMs like 27C64?
AT28C64-20TC is not a direct pin-compatible replacement for 27C64 EPROMs due to differing pin functions: 27C64 uses VPP for programming and lacks RDY/BUSY and WE pins, while AT28C64-20TC uses WE for write control and RDY/BUSY for status. However, AT28C64-20TC follows JEDEC-standard byte-wide pinout (identical to 6264 SRAM), allowing PCB reuse if the original design accommodated SRAM-style control signals. AT28C64-20TC replaces 27C64 in system-level functionality but requires matching CE/OE/WE logic - not blind socket replacement.
What write protection mechanisms are built into AT28C64-20TC?
AT28C64-20TC incorporates three hardware-enforced write protection layers: (1) VCC sense - write inhibited if supply drops below ~3.8 V; (2) power-on delay - automatic 5 ms lockout after VCC stabilization; and (3) triple-signal inhibit - write blocked unless CE is low, OE is high, and WE is low simultaneously. These features prevent spurious writes during power transients, reset sequences, or bus contention. AT28C64-20TC implements all three protections natively - no external components or firmware checks are required to ensure data integrity.
AT28C64-20TC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-TSSOP (0.465", 11.80mm Width)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 200 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSOP
AT28C64-20TC FAQ
1.How can I place an order for AT28C64-20TC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64-20TC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64-20TC reliable?
The price and inventory of AT28C64-20TC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64-20TC is usually 5 days.
3.What payment methods are accepted for AT28C64-20TC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64-20TC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64-20TC?
AT28C64-20TC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64-20TC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64-20TC?
For technical support, including AT28C64-20TC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64-20TC requirements.
6.How does Aetrix verify that AT28C64-20TC is sourced from the original manufacturer or authorized distributors?
All AT28C64-20TC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64-20TC meets industry standards.
7.What is the process for return or replacement of AT28C64-20TC?
All AT28C64-20TC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64-20TC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64-20TC part is unused and in its original packaging.
Return procedure for AT28C64-20TC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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