Microchip Technology AT28C64B-15JC
- Part No.:
- AT28C64B-15JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28C64B-15JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,183
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C64B-15JC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, hardware/software data protection, and page write capability supporting up to 64-byte writes in ≤10 ms. It operates on single 5 V ±10% supply and targets nonvolatile storage in industrial control panels requiring field-upgradable firmware parameters.
For engineers reviewing the AT28C64B-15JC datasheet, AT28C64B-15JC pinout, AT28C64B-15JC application, or AT28C64B-15JC equivalent, key selection criteria include verified 150 ns tACC timing, CMOS/TTL-compatible I/O, JEDEC-compliant 32-pin PLCC package, DATA polling and toggle bit for write completion detection, and industrial temperature range support (-40°C to +85°C).
Technical Context
The AT28C64B-15JC implements a static RAM-like interface with dual-line chip enable (CE) and output enable (OE) control, enabling bus contention avoidance in multi-peripheral systems. Its internal 64-byte page register latches address and data during page write operations, freeing the address/data bus after initiation.
Write completion is confirmed via two independent methods: DATA polling (I/O7 complement inversion) and toggle bit (I/O6 state alternation), both usable at any point during the write cycle. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE logic gating.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - supports full firmware parameter tables or calibration data sets without external expansion. |
| Read Access Time | 150 ns max - enables direct replacement of SRAM in legacy 8-bit microcontroller systems with no timing redesign. |
| Page Write Cycle | 10 ms max (standard) - allows bulk configuration updates with minimal host CPU intervention and deterministic latency. |
| Supply Voltage | 5 V ±10% - compatible with standard TTL/CMOS logic rails and eliminates need for auxiliary voltage regulators. |
| Operating Temperature | -40°C to +85°C - qualified for industrial automation, motor drives, and outdoor metering applications. |
| Endurance | 100,000 write cycles - supports frequent recalibration or logging in programmable logic controllers (PLCs). |
| Data Retention | 10 years - ensures long-term reliability of stored calibration coefficients or security keys without refresh. |
Pinout & Package
AT28C64B-15JC uses a 32-lead Plastic J-leaded Chip Carrier (PLCC) package per JEDEC MS-016, Variation AE. Pins 1 and 17 are designated "Don't Connect" (DC) and must remain unconnected. Pin 1 identifier is marked by a corner chamfer.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; A6–A12 define page boundaries for 64-byte page writes. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; I/O7 used for DATA polling, I/O6 for toggle bit detection during write cycles. |
| CE | Chip Enable | Active-low global device select; combined with OE/WE to determine read/write/standby modes per JEDEC timing table. |
| OE | Output Enable | Active-low output gate control; high during write cycles to place outputs in high-impedance state and prevent bus conflicts. |
| WE | Write Enable | Active-low write strobe; falling edge latches address, rising edge latches data in byte or page write mode. |
| VCC / GND | Power Supply | Single 5 V supply with CMOS standby current <100 µA - reduces system-level power budget in always-on monitoring nodes. |
| NC / DC | No Connect / Don't Connect | Pins 1 and 17 are internally unused and must be left floating; violation risks latch-up or undefined behavior. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC Byte-wide Pinout | Direct drop-in compatibility with industry-standard 27C64/27C256 socket footprints and PCB layouts. |
| Software Data Protection (SDP) | User-configurable 3-byte command sequence (AAh/55h/A0h) enables/disables write protection without hardware changes. |
| Page Write Operation | Internal 64-byte latch allows sequential loading of 1–64 bytes within 150 µs intervals, reducing host overhead vs. byte-by-byte writes. |
| Hardware Write Inhibit | VCC sense, 5 ms power-on delay, and noise filtering eliminate need for external reset supervisors or RC timing circuits. |
| Device Identification Area | Dedicated 64-byte EEPROM region (1FC0H–1FFFH) accessible at 12 V on A9 for unique serial number or revision tracking. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing user-adjustable PID loop gains, alarm thresholds, and sensor linearization tables in programmable logic controllers deployed in factory environments. IC Role / Device Role / Timing Role: Nonvolatile parameter repository accessed during boot and runtime via 8-bit parallel bus; 150 ns read access ensures real-time response to control interrupts. Use Value: Eliminates battery-backed SRAM and associated maintenance; 100,000-cycle endurance supports weekly calibration updates over 10+ years. |
Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable diagnostic equipment subject to regulatory traceability requirements. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage accessed only during device initialization; software data protection prevents accidental overwrite during field servicing. Use Value: Device ID area (1FC0H–1FFFH) stores unique unit serial numbers at 12 V, satisfying FDA UDI compliance for medical hardware. |
| Automotive ECU Parameter Tables | Telecom Line Card Firmware Patch Storage |
|
Use Scenario: Storing adaptive learning values (e.g., fuel trim corrections) and emission control maps in engine control units operating across -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-grade EEPROM interfaced directly to 8051 or C166 derivatives; 10-year data retention guarantees map integrity over vehicle lifetime. Use Value: Hardware VCC-sense protection prevents corruption during cold-cranking voltage dips below 4.5 V, ensuring safe ECU restart. |
Use Scenario: Hosting hot-swappable firmware patches for DSLAM line cards where field upgrades must occur without chassis reboot. IC Role / Device Role / Timing Role: Parallel-boot memory mapped into processor address space; page write enables 64-byte patch segments to load in ≤10 ms without interrupting active traffic. Use Value: Toggle bit detection allows host CPU to poll I/O6 asynchronously during write, avoiding fixed-delay timeouts and improving upgrade throughput. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST M28W640ECB90N1 | 64 Mbit density, 90 ns access, 3.3 V core (5 V I/O tolerant), SOIC-44 package | Higher density and speed but requires level-shifting for pure 5 V systems; not pin-compatible with AT28C64B-15JC's PLCC-32 | Select when migrating to higher-density nonvolatile storage with mixed-voltage design flexibility. |
| Microchip 25LC640-I/P | 64 Kbit SPI interface, 5 V operation, PDIP-8 package, 5 ms write cycle | Serial interface reduces pin count but increases software overhead; lacks page write and hardware write inhibit features | Select for space-constrained designs where board real estate outweighs parallel bus performance requirements. |
Compared with ST M28W640ECB90N1 and Microchip 25LC640-I/P, the AT28C64B-15JC delivers JEDEC-standard parallel compatibility, deterministic 10 ms page writes, and robust hardware-based write protection-making it optimal for retrofitting legacy 8-bit systems without layout or firmware rework.
Availability
AT28C64B-15JC is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostic instruments, automotive ECUs, and telecom line cards requiring stable component supply and long-term lifecycle support.
Supply support for AT28C64B-15JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28C64B belongs to Atmel's parallel EEPROM product line, designed specifically for legacy system upgrades and industrial applications demanding pin-compatible replacements for EPROMs and battery-backed SRAMs.
FAQ
What is the maximum read access time specified for the AT28C64B-15JC?
The AT28C64B-15JC has a guaranteed maximum read access time (tACC) of 150 ns under commercial and industrial temperature ranges. This value is tested and characterized per AC Read Characteristics table in the official datasheet, and applies specifically to the -15 speed grade. The AT28C64B-15JC achieves this timing with 5 V ±10% supply and load conditions matching CL = 5 pF.
Does the AT28C64B-15JC support page write operations, and what is the maximum page size?
Yes, the AT28C64B-15JC supports page write operations with a maximum page size of 64 bytes. The device includes an internal 64-byte page register that latches addresses and data, allowing sequential loading of 1–64 bytes within 150 µs intervals. All bytes in a page write must reside on the same page defined by A6–A12, and the full page write completes in ≤10 ms (standard version).
How does hardware data protection work on the AT28C64B-15JC?
Hardware data protection on the AT28C64B-15JC includes four mechanisms: (1) VCC sense that inhibits writes if supply drops below ~3.8 V; (2) automatic 5 ms power-on delay before write enable; (3) logical write inhibit when CE is high, OE is low, or WE is high; and (4) noise filtering rejecting input pulses shorter than 15 ns. These features operate independently of firmware and require no host intervention.
Can the AT28C64B-15JC be used in industrial temperature applications?
Yes, the AT28C64B-15JC is rated for industrial temperature operation from -40°C to +85°C. This rating is confirmed in the "DC and AC Operating Range" table of the datasheet and applies to all variants ending in "JI" or "JC". The "JC" suffix specifically denotes the 32-lead PLCC package with industrial temperature qualification.
What package type is used for the AT28C64B-15JC, and are there any special connection requirements?
The AT28C64B-15JC uses a 32-lead Plastic J-leaded Chip Carrier (PLCC) package (package code 32J). Pins 1 and 17 are designated "Don't Connect" (DC) and must remain unconnected in the PCB layout. The package conforms to JEDEC MS-016, Variation AE, and requires standard PLCC socket or reflow soldering profiles compatible with lead-free assembly.
AT28C64B-15JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 150 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28C64B-15JC FAQ
1.How can I place an order for AT28C64B-15JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64B-15JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64B-15JC reliable?
The price and inventory of AT28C64B-15JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64B-15JC is usually 5 days.
3.What payment methods are accepted for AT28C64B-15JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64B-15JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64B-15JC?
AT28C64B-15JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64B-15JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64B-15JC?
For technical support, including AT28C64B-15JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64B-15JC requirements.
6.How does Aetrix verify that AT28C64B-15JC is sourced from the original manufacturer or authorized distributors?
All AT28C64B-15JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64B-15JC meets industry standards.
7.What is the process for return or replacement of AT28C64B-15JC?
All AT28C64B-15JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64B-15JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64B-15JC part is unused and in its original packaging.
Return procedure for AT28C64B-15JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C64B-15JC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

