Microchip Technology AT28C64B-15JU

Overview

AT28C64B-15JU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, 10 ms page write cycle, and hardware/software data protection. It operates from a single 5V ±10% supply and supports industrial temperature range (–40°C to +85°C) for embedded control, firmware storage, and configuration memory in programmable logic systems.

For engineers reviewing the AT28C64B-15JU datasheet, AT28C64B-15JU pinout, AT28C64B-15JU application, or AT28C64B-15JU equivalent, key selection criteria include its 64-byte page write capability, DATA polling and toggle bit for write completion detection, CMOS/TTL compatibility, and green (Pb/halide-free) 32-lead PLCC packaging.

Technical Context

The AT28C64B-15JU implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches address and data during write cycles, freeing the bus for concurrent operations.

Write completion is verified via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle bit detection-both functional during active programming. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE state-dependent write inhibition.

Key Specifications

Pinout & Package

AT28C64B-15JU is packaged in a 32-lead Plastic J-Leaded Chip Carrier (PLCC), compliant with JEDEC MS-016 Variation AE. Pin 1 is marked by a corner notch; pins 1 and 17 are Don't Connect (DC).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-15JU, AT28C64B-15PU offers identical functionality in a through-hole package but demands board-level redesign, while AT28HC64B-15JU delivers 5× faster page writes without layout changes-making it ideal for high-throughput programming stations or real-time update scenarios.

Availability

AT28C64B-15JU is available at Aetrix Electronics and suitable for industrial control systems, embedded instrumentation, telecom infrastructure, and legacy system upgrades requiring stable component supply and long-lifecycle support.

Supply support for AT28C64B-15JU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT28C64B family.

The AT28C64B series was designed as a drop-in SRAM-replacement EEPROM for 8-bit microcontroller systems requiring nonvolatile storage with zero wait-state reads and simple parallel bus interfacing.

FAQ

What is the maximum page write size supported by the AT28C64B-15JU?

The AT28C64B-15JU supports a maximum page write size of 64 bytes. This is enabled by its internal 64-byte page register, which latches address and data during a single write cycle. All bytes written in one page operation must reside within the same 64-byte boundary defined by address bits A6–A12. The AT28C64B-15JU does not support larger block writes or sector erases-each page write is independent and self-timed.

How does hardware data protection work on the AT28C64B-15JU?

Hardware data protection on the AT28C64B-15JU operates through four mechanisms: (1) VCC sense circuitry inhibits writes if supply drops below ~3.8 V; (2) a 5 ms internal timer delays write enable after power-up; (3) write is blocked unless CE is low, OE is high, and WE is low simultaneously; and (4) input noise filters reject pulses shorter than 15 ns on CE or WE. These features ensure the AT28C64B-15JU remains immune to spurious writes during power transients or EMI events.

Can the AT28C64B-15JU be used as a direct replacement for SRAM in an existing design?

Yes-the AT28C64B-15JU uses a JEDEC-approved byte-wide pinout and behaves electrically like a Static RAM during read cycles: CE and OE low with WE high asserts data on I/O0–I/O7 within 150 ns. No external components are needed for read operation. However, write timing differs: page writes require 10 ms internal execution, and software/hardware protection must be managed. The AT28C64B-15JU is a functional read-compatible replacement but requires firmware adaptation for writes.

What is the purpose of the extra 64-byte identification area in the AT28C64B-15JU?

The AT28C64B-15JU includes an additional 64-byte EEPROM region (addresses 1FC0H–1FFFH) reserved for device-specific data such as serial numbers, calibration constants, or manufacturing traceability codes. Access requires raising A9 to 12.0 V ±0.5 V-this high-voltage enable prevents accidental writes during normal 5V operation. The AT28C64B-15JU's identification area functions identically to main memory for reads/writes once enabled, supporting unique device management in automated test and field service workflows.

Does the AT28C64B-15JU support both CE-controlled and WE-controlled write operations?

Yes-the AT28C64B-15JU supports both CE-controlled and WE-controlled write modes, as defined in its AC Write Waveforms (Sections 15.1 and 15.2). In CE-controlled mode, a low pulse on CE (with WE low and OE high) initiates the write; in WE-controlled mode, a low pulse on WE (with CE low and OE high) initiates it. Both methods latch address on the falling edge of the active control signal and data on its rising edge. The AT28C64B-15JU's dual-control flexibility allows seamless integration into diverse bus architectures without redesign.