Microchip Technology AT28C64B-15JU-235

Overview

AT28C64B-15JU-235 from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, 10 ms page write cycle, and hardware/software data protection. It operates from a single 5V ±10% supply, supports industrial temperature range (–40°C to +85°C), and integrates a 64-byte page register for efficient in-system programming in embedded control and instrumentation applications.

For engineers reviewing the AT28C64B-15JU-235 datasheet, AT28C64B-15JU-235 pinout, AT28C64B-15JU-235 application, or AT28C64B-15JU-235 equivalent, key selection criteria include verified page write timing (10 ms max), DATA polling and toggle bit write completion detection, CMOS/TTL compatibility, VCC sense and noise-filtered write inhibit, and green (Pb/halide-free) PLCC-32 packaging.

Technical Context

The AT28C64B-15JU-235 implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page latch allows up to 64 bytes to be loaded within 150 µs per byte before automatic internal programming begins.

Write completion is confirmed via I/O7 DATA polling (complement-to-data behavior) or I/O6 toggle bit detection-both operable at any point during the write cycle. Hardware protection includes VCC sense (<3.8 V inhibition), 5 ms power-on delay, and 15 ns noise filtering on WE/CE inputs.

Key Specifications

Pinout & Package

AT28C64B-15JU-235 is supplied in a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package, RoHS-compliant and Pb/halide-free per ordering code suffix "JU". Pin 1 is marked by a corner notch; pins 1 and 17 are no-connect (NC) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-15JU-235, AT28C64B-15PU offers identical functionality but inferior thermal and mechanical reliability in production, while AT28HC64B-15JU delivers measurable write-speed improvement at the cost of verifying tighter timing compliance in the host controller.

Availability

AT28C64B-15JU-235 is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, and telecom line card firmware patching requiring stable component supply across extended product lifecycles.

Supply support for AT28C64B-15JU-235 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C64B product line was designed for reliable, in-system programmable parallel EEPROM replacement in legacy 8-bit embedded systems requiring industrial temperature operation and robust data integrity.

FAQ

What is the maximum page write cycle time for AT28C64B-15JU-235?

The maximum page write cycle time for AT28C64B-15JU-235 is 10 ms under standard operation. This value is guaranteed across the industrial temperature range (–40°C to +85°C) and applies to all 1–64 byte writes within a single page. The AT28C64B-15JU-235 does not support the optional 2 ms page write mode - that feature is exclusive to the AT28HC64B variant.

How does hardware write protection function on AT28C64B-15JU-235?

Hardware write protection on AT28C64B-15JU-235 operates through four mechanisms: (1) VCC sense inhibits writes if supply drops below ~3.8 V; (2) a 5 ms internal power-on delay prevents writes until VCC stabilizes; (3) write is blocked if OE is low, CE is high, or WE is high; and (4) input noise pulses <15 ns on WE or CE are filtered out. These features collectively prevent corruption during brown-out or EMI events.

Can AT28C64B-15JU-235 be used as a drop-in replacement for standard SRAM in existing designs?

Yes - AT28C64B-15JU-235 uses JEDEC-approved byte-wide pinout and matches SRAM timing for read operations (150 ns access, compatible CE/OE/WE control). However, write cycles require explicit host coordination via DATA polling or toggle bit detection, unlike SRAM's transparent write. No PCB changes are needed for read-only or controlled-write integration.

What is the purpose of the 64-byte device identification area in AT28C64B-15JU-235?

The 64-byte device identification area (addresses 1FC0H–1FFFH) in AT28C64B-15JU-235 provides dedicated nonvolatile storage for calibration data, serial numbers, or manufacturing traceability. Access requires raising A9 to 12.0 V ±0.5 V - a one-time hardware enable that isolates this region from normal 5V operation, preventing accidental overwrite during routine use.

Does AT28C64B-15JU-235 support both CE-controlled and WE-controlled write modes?

Yes - AT28C64B-15JU-235 supports both CE-controlled and WE-controlled write initiation, as defined in its AC write waveforms. Either signal can serve as the primary write strobe, provided the other remains asserted appropriately (e.g., CE low during WE-controlled write). The device latches address on the later falling edge and data on the first rising edge of CE or WE, ensuring deterministic timing regardless of control method.