Microchip Technology AT28C64B-15PU

Overview

AT28C64B-15PU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), operates on single 5V ±10% supply, and targets nonvolatile storage in industrial control panels requiring reliable field-updatable configuration memory.

For engineers reviewing the AT28C64B-15PU datasheet, AT28C64B-15PU pinout, AT28C64B-15PU application, or AT28C64B-15PU equivalent, key selection criteria include page write timing (10 ms max), CMOS standby current (100 µA), DATA polling/Toggle Bit end-of-write detection, and industrial temperature range (−40°C to +85°C).

Technical Context

The AT28C64B-15PU implements a static RAM-compatible interface with dual-line chip enable (CE) and output enable (OE) control to prevent bus contention. Its internal 64-byte page register latches addresses and data during write cycles, freeing the address/data bus for concurrent operations.

Write completion is verified via I/O7 DATA polling (complement-to-data toggle) or I/O6 Toggle Bit behavior, both usable at any point during tWC. Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs.

Key Specifications

Pinout & Package

AT28C64B-15PU uses a 28-lead PDIP (0.600" wide) package per JEDEC MS-011 AB standard, with 0.100" lead pitch and through-hole mounting compatibility.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-15PU, AT28C64B-15SU offers identical electrical performance in a surface-mount package for automated assembly, while AT28HC64B-15PU delivers faster 2 ms page writes for time-critical updates-both retain full software/hardware data protection and JEDEC pin compatibility.

Availability

AT28C64B-15PU is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom infrastructure, and automotive body electronics requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for AT28C64B-15PU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and continues to manufacture, support, and qualify legacy Atmel EEPROM products including the AT28C64B series for industrial and automotive applications.

The AT28C64B product line was designed for robust, pin-compatible replacement of EPROM and battery-backed SRAM in legacy 8-bit systems requiring field-updatable nonvolatile storage with minimal design change.

FAQ

What is the maximum page write cycle time for AT28C64B-15PU?

The AT28C64B-15PU has a maximum page write cycle time of 10 ms under standard operation. This value is guaranteed across the full industrial temperature range (−40°C to +85°C) and applies to all 1–64 byte writes within a single 64-byte page boundary defined by address bits A6–A12. The AT28C64B-15PU does not support the optional 2 ms page write mode found in the AT28HC64B variant.

How does hardware data protection function in AT28C64B-15PU?

AT28C64B-15PU implements four hardware safeguards: (1) VCC sense inhibits writes below 3.8 V, (2) a 5 ms power-on delay prevents writes until supply stabilizes, (3) write inhibition occurs if OE is low, CE is high, or WE is high, and (4) noise filtering rejects sub-15 ns pulses on WE/CE. These mechanisms operate independently of firmware and ensure AT28C64B-15PU remains protected during power transients and EMI events.

Can AT28C64B-15PU be used in place of standard SRAM in existing designs?

Yes, AT28C64B-15PU is designed for drop-in replacement of 8K × 8 SRAM in read operations due to its identical JEDEC byte-wide pinout and SRAM-like access protocol. However, write cycles require explicit WE/CE timing control and end-of-write detection via DATA polling or Toggle Bit-unlike SRAM, AT28C64B-15PU does not support true simultaneous read/write and requires host firmware adaptation for write sequencing.

What is the purpose of the 64-byte device identification area in AT28C64B-15PU?

The AT28C64B-15PU includes an additional 64-byte EEPROM region (addresses 1FC0h–1FFFh) accessible only when A9 is raised to 12.0 V ±0.5 V. This area is intended for permanent device serialization, calibration data storage, or manufacturing traceability-separate from main memory-and retains data for 10 years at 85°C, matching the primary array's retention specification.

Does AT28C64B-15PU support both CE-controlled and WE-controlled write operations?

Yes, AT28C64B-15PU supports both CE-controlled and WE-controlled write initiation as defined in its AC Write Waveforms (sections 15.1 and 15.2). The device latches address on the last falling edge of CE or WE and latches data on the first rising edge of either signal. This dual-control flexibility allows integration into diverse 8-bit bus architectures where either chip select or write strobe may serve as the primary timing reference for write cycles.