Microchip Technology AT28C64B-15SC

Overview

AT28C64B-15SC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, single 5 V ±10% supply, and hardware/software data protection-used in industrial control firmware storage and embedded configuration memory.

For engineers reviewing the AT28C64B-15SC datasheet, AT28C64B-15SC pinout, AT28C64B-15SC application, or AT28C64B-15SC equivalent, key selection criteria include page write capability (1–64 bytes), DATA polling/toggle bit write completion detection, CMOS/TTL compatibility, 100,000 endurance cycles, and industrial temperature support (−40°C to +85°C).

Technical Context

The AT28C64B-15SC operates as a parallel-access nonvolatile memory with static RAM-like read/write interface logic-requiring no external timing components. Its internal 64-byte page register enables burst writes without bus hold, while address latching on CE/WE falling edge and data latching on rising edge define precise byte/page write sequencing.

Write completion is verified via I/O7 DATA polling (complement-to-data during write, true data after completion) or I/O6 toggle bit behavior-both usable at any point during tWC (10 ms max). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, and noise filtering (<15 ns pulses ignored).

Key Specifications

Pinout & Package

AT28C64B-15SC is supplied in a 28-lead, 0.300" wide plastic gull-wing small outline (SOIC) package per JEDEC MS-013, with 1.27 mm lead pitch and surface-mount footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with ST M28W640ECB90N1 and Microchip 28C64B-15J, the AT28C64B-15SC offers optimal fit for existing 5 V, SOIC-based industrial designs-preserving board layout, power architecture, and timing margins without compromise on endurance or write verification methods.

Availability

AT28C64B-15SC is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, automotive body electronics, and legacy HMI platforms requiring stable component supply and long-term lifecycle support.

Supply support for AT28C64B-15SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.

The AT28C64B belongs to Atmel's parallel EEPROM product line, designed specifically for drop-in replacement of battery-backed SRAM in industrial and automotive applications demanding high reliability and simple 8-bit bus integration.

FAQ

What is the maximum page write size supported by the AT28C64B-15SC?

The AT28C64B-15SC supports up to 64 bytes per page write operation. All bytes must reside within the same 64-byte page boundary defined by address bits A6–A12. Each subsequent byte must be loaded within 150 µs of the prior one; exceeding this interval triggers automatic internal programming. This capability is confirmed in the "Page Write" section of the AT28C64B-15SC datasheet (Rev. 0270I–PEEPR–08/03, p.3).

Does the AT28C64B-15SC require a 12 V supply for normal operation?

No, the AT28C64B-15SC operates solely from a 5 V ±10% supply under standard read/write conditions. The 12 V requirement applies exclusively to accessing the 64-byte device identification area (addresses 1FC0H–1FFFH), which is optional and not used in routine operation. All functional specifications-including 150 ns access time and page write-are guaranteed at 5 V.

How does DATA polling work on the AT28C64B-15SC during a write cycle?

During a write cycle, reading the last written byte returns the complement of that data on I/O7. Once the internal programming completes, true data appears on all I/O lines including I/O7. This behavior allows the host MCU to poll I/O7 in a tight loop without fixed delays. The AT28C64B-15SC datasheet confirms this mechanism is valid for both byte and page writes (p.3, "DATA POLLING").

Can the AT28C64B-15SC be used as a direct replacement for SRAM in an existing design?

Yes-the AT28C64B-15SC uses JEDEC-approved byte-wide pinout and behaves like SRAM during reads (CE/OE low, WE high) and writes (CE/WE controlled). No external timing components are needed. However, write cycles require explicit end-of-write detection (via DATA polling or toggle bit), unlike volatile SRAM. This difference must be implemented in firmware but preserves full hardware compatibility.

What is the purpose of the software data protection (SDP) feature in the AT28C64B-15SC?

The SDP feature prevents inadvertent writes using a user-configurable 3-byte unlock sequence (AAh → 55h → A0h). Once enabled, all writes require repeating this sequence before data-ensuring immunity to noise-induced or power-related spurious writes. The AT28C64B-15SC ships with SDP disabled, and the command sequence is detailed in the "Software Data Protection Algorithms" section (p.9–10) of its datasheet.