Microchip Technology AT28C64B-15TU

Overview

AT28C64B-15TU from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, and hardware/software data protection. It supports page write (1–64 bytes), DATA polling and toggle-bit write completion detection, and operates from a single 5V ±10% supply in industrial temperature range (–40°C to +85°C) for embedded system configuration storage.

For engineers reviewing the AT28C64B-15TU datasheet, AT28C64B-15TU pinout, AT28C64B-15TU application, or AT28C64B-15TU equivalent, key selection criteria include verified page-write timing (10 ms max), CMOS standby current (100 µA), endurance (100,000 cycles), software data protection enable/disable sequence, and TSOP-28 package compatibility with legacy SRAM-based memory interfaces.

Technical Context

The AT28C64B-15TU implements a static RAM-compatible interface: reads occur when CE and OE are low and WE is high; writes initiate on falling WE or CE with OE high. Its internal 64-byte page register latches address and data during page write, freeing the bus for concurrent operations.

Write completion is confirmed via dual methods: DATA polling (I/O7 complement-to-data behavior) and toggle-bit detection (I/O6 toggling until write ends). Hardware protection includes VCC sense (<3.8 V inhibit), 5 ms power-on delay, noise filtering (<15 ns pulse rejection), and CE/OE/WE state-dependent write inhibition.

Key Specifications

Pinout & Package

AT28C64B-15TU is supplied in a 28-lead Plastic Thin Small Outline Package (TSOP), Type I, 8 mm × 13.4 mm body, with gull-wing leads and pin 1 identifier marking. Pin pitch is 0.55 mm; lead coplanarity ≤0.10 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-15TU, the PDIP variant offers mechanical robustness and hand-soldering flexibility, while the SOIC variant provides tighter board area usage and proven reflow yield-both retain identical timing, protection features, and 150 ns access, making them functionally interchangeable where package constraints allow.

Availability

AT28C64B-15TU is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, telecom infrastructure, and automotive electronics requiring stable component supply across extended product lifecycles.

Supply support for AT28C64B-15TU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for the AT28C64B family as part of its legacy parallel EEPROM portfolio.

The AT28C64B series was designed for embedded systems needing reliable, pin-compatible nonvolatile memory with zero external components for read/write operation-targeting applications where SRAM+backup battery is impractical.

FAQ

What is the maximum page write cycle time for AT28C64B-15TU?

The AT28C64B-15TU has a maximum page write cycle time of 10 ms under standard operation. This value is guaranteed across the industrial temperature range (–40°C to +85°C) and defines the minimum interval required before initiating the next write operation. The datasheet notes an optional 2 ms version exists (AT28HC64BF), but that is a distinct part number-not applicable to AT28C64B-15TU.

Does AT28C64B-15TU support both hardware and software write protection?

Yes, AT28C64B-15TU implements dual-layer protection: hardware protection includes VCC sensing (<3.8 V inhibit), 5 ms power-on delay, and noise filtering on WE/CE inputs; software protection is enabled via a three-byte command sequence (AAh → 55h → A0h) written to specific addresses. Both mechanisms operate independently and concurrently to prevent unintended writes during power transitions or firmware errors.

Can AT28C64B-15TU be used as a direct replacement for standard SRAM in existing designs?

Yes, AT28C64B-15TU uses a JEDEC-approved byte-wide pinout and behaves electrically like a Static RAM during read cycles (CE/OE low, WE high), allowing drop-in replacement in many 28-pin SRAM sockets. However, write timing differs: writes require proper WE/CE/OE handshaking and write completion detection (DATA polling or toggle bit), so firmware must be updated to manage write cycles-not just address/data bus timing.

What package type is used for AT28C64B-15TU?

AT28C64B-15TU is packaged in a 28-lead Plastic Thin Small Outline Package (TSOP), Type I, with dimensions 8 mm × 13.4 mm and gull-wing leads. This surface-mount package is optimized for automated assembly and offers lower profile than PDIP or SOIC variants, making it suitable for space-constrained industrial and telecom modules.

How is write completion detected on AT28C64B-15TU?

AT28C64B-15TU supports two independent, hardware-verified methods: DATA polling (monitoring I/O7 - it returns complement of written data until completion, then true data) and toggle-bit detection (monitoring I/O6 - it toggles between 0 and 1 during write, then stabilizes). Either method can be initiated at any time during the write cycle and requires no additional hardware, enabling robust firmware-driven write synchronization.