Microchip Technology AT28C64B-15TU-T

Overview

AT28C64B-15TU-T from Microchip Technology (formerly Atmel) is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 150 ns read access time, page write capability (1–64 bytes), and single 5V ±10% supply operation. It features hardware and software data protection, DATA polling and toggle-bit write completion detection, and industrial temperature support (−40°C to +85°C), used in embedded system configuration storage and firmware parameter retention.

For engineers reviewing the AT28C64B-15TU-T datasheet, AT28C64B-15TU-T pinout, AT28C64B-15TU-T application, or AT28C64B-15TU-T equivalent, key selection criteria include verified page write timing (10 ms max), CMOS/TTL compatibility, VCC sense-based write inhibit, 100,000 endurance cycles, and TSOP-28 package mechanical dimensions for PCB layout validation.

Technical Context

The AT28C64B-15TU-T operates as a drop-in parallel memory replacement for SRAM in legacy systems, supporting standard read cycles with CE/OE/WE control logic and automatic internal latching of address and data during page writes. Its architecture includes a 64-byte page register, internal write timer, and dual write-completion detection (I/O7 DATA polling and I/O6 toggle bit).

Hardware data protection relies on VCC sensing (<3.8 V inhibits write), 5 ms power-on delay, noise filtering (<15 ns pulses rejected), and active-level control (OE low / CE high / WE high disables write). Software Data Protection (SDP) is user-enabled via a three-byte command sequence at addresses 1555H/0AAAH/1555H, persisting across power cycles.

Key Specifications

Pinout & Package

AT28C64B-15TU-T is packaged in a 28-lead Plastic Thin Small Outline Package (TSOP, Type I, 8 × 13.4 mm), compliant with JEDEC MO-183, with gull-wing leads and pin 1 identifier marking. Pin pitch is 0.55 mm; body thickness ≤1.20 mm; lead coplanarity ≤0.10 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-15PU, the AT28C64B-15TU-T offers lower profile and automated assembly compatibility; compared with MN66C64-15, it delivers certified write security and traceable device identity-critical for medical and industrial certifications.

Availability

AT28C64B-15TU-T is available at Aetrix Electronics and suitable for industrial PLCs, automotive body control modules, telecom line cards, and medical diagnostic equipment requiring stable component supply across extended product lifecycles.

Supply support for AT28C64B-15TU-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT28C64B family. The company specializes in microcontrollers, analog, and nonvolatile memory solutions for industrial, automotive, and communications markets.

The AT28C64B series was designed as a pin- and function-compatible upgrade to earlier EPROM and battery-backed SRAM solutions, targeting legacy system modernization with zero-changes to existing 5V parallel bus architectures.

FAQ

What is the maximum page write cycle time for AT28C64B-15TU-T?

The maximum page write cycle time for AT28C64B-15TU-T is 10 ms under standard operation, as specified in the official Atmel/Microchip datasheet (document 0270L–PEEPR–2/09). This value applies to all page sizes (1–64 bytes) and is measured from the final WE high-to-low transition until write completion. The 2 ms option referenced in the datasheet applies only to the AT28HC64BF variant and is not valid for AT28C64B-15TU-T.

Does AT28C64B-15TU-T support software data protection (SDP)?

Yes, AT28C64B-15TU-T fully supports software data protection (SDP) as described in Section 4.6.2 of its datasheet. SDP is enabled or disabled using a precise three-byte command sequence written to specific addresses (1555H, 0AAAH, then 1555H), and remains active across power cycles. The AT28C64B-15TU-T ships with SDP disabled by default, and the feature is implemented in silicon-not dependent on external components or firmware.

What package type is used for AT28C64B-15TU-T?

AT28C64B-15TU-T uses a 28-lead Plastic Thin Small Outline Package (TSOP, Type I), designated as "28T" in Microchip's ordering information. Its dimensions are 8.0 × 13.4 mm, with 0.55 mm lead pitch and gull-wing leads. This surface-mount package complies with JEDEC MO-183 and is optimized for automated PCB assembly in space-constrained industrial applications.

How is write completion detected on AT28C64B-15TU-T?

AT28C64B-15TU-T provides two independent hardware methods: DATA polling (monitoring complement-to-data state on I/O7) and toggle-bit detection (observing oscillation on I/O6). Both methods are functional during any write cycle (byte or page) and require no additional timing components. The toggle bit stops toggling and I/O7 returns true data once the internal write timer completes-typically within the guaranteed 10 ms window.

Is AT28C64B-15TU-T compatible with TTL and CMOS logic levels?

Yes, AT28C64B-15TU-T features CMOS and TTL compatible inputs and outputs, as explicitly stated in its datasheet Features section. Input thresholds meet TTL standards (VIL ≤ 0.8 V, VIH ≥ 2.0 V), and output drive strength satisfies both TTL (IOL = 2.1 mA, VOL ≤ 0.4 V) and CMOS (IOH = −400 µA, VOH ≥ 2.4 V) loading conditions-enabling direct interface with legacy 5V microcontrollers, FPGAs, and ASICs without level shifters.