Microchip Technology AT28C64E-12PC

Overview

AT28C64E-12PC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 120 ns read access time, 200 µs fast byte write capability, and JEDEC-standard 28-pin PDIP package. It operates at 5V ±10%, supports CMOS/TTL-compatible I/O, and delivers 30 mA active current and 100 µA standby current for embedded microcontroller systems requiring nonvolatile configuration storage.

For engineers reviewing the AT28C64E-12PC datasheet, AT28C64E-12PC pinout, AT28C64E-12PC application, or AT28C64E-12PC equivalent, key selection criteria include verified 200 µs write cycle timing, RDY/BUSY open-drain signaling, DATA polling support on I/O7, JEDEC byte-wide pin compatibility, and industrial-grade (-40°C to +85°C) operation in the PDIP package.

Technical Context

The AT28C64E-12PC implements self-timed byte write cycles using internal address/data latches and an integrated control timer, eliminating external timing components. Its READY/BUSY output and DATA polling (I/O7 complement during write) provide dual, hardware-synchronized write completion detection methods.

It features VCC sense (write inhibit below 3.8 V), 5 ms power-on delay, and triple-level write protection via CE/OE/WE logic states. The device includes 32 bytes of dedicated identification memory accessible at 1FE0H–1FFFH using A9 = 12 V, and supports full-chip erase via 12 V on OE with WE pulse.

Key Specifications

Pinout & Package

AT28C64E-12PC uses a 28-lead, 0.600" wide plastic DIP (PDIP) package per JEDEC MS-011 AB. Pin 1 is RDY/BUSY (open-drain); pins 10, 11, 12, 13, 14, 15, 16, 17 are I/O0–I/O7; pins 18–28 and 1–9 are address, control, and power terminals as defined below.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel EEPROM applications.

Compared with AT28C64B-12PC, the AT28C64E-12PC delivers 5× faster writes and 10× higher endurance-critical for dynamic calibration-but shares identical footprint and interface logic. Versus ST M28W640ECB90N1, it offers drop-in 5 V compatibility and zero firmware changes, though at lower density and slower access.

Availability

AT28C64E-12PC is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, automotive body control modules, and automated test systems requiring stable component supply across extended product lifecycles.

Supply support for AT28C64E-12PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial, automotive, and consumer applications.

The AT28C64E-12PC belongs to Atmel's parallel EEPROM product line, designed specifically for 5 V microprocessor systems needing reliable, pin-compatible, byte-erasable nonvolatile storage with minimal external circuitry.

FAQ

What is the maximum write cycle time for AT28C64E-12PC?

The AT28C64E-12PC guarantees a maximum byte write cycle time of 200 µs, confirmed in the AC Write Characteristics table. This is a key differentiator from the standard AT28C64B variant (1 ms). The 200 µs timing applies across the full industrial temperature range (-40°C to +85°C) and is internally self-timed using an on-chip control timer-no external timing components are needed. AT28C64E-12PC achieves this performance while maintaining full compatibility with standard 5 V microprocessor buses.

Does AT28C64E-12PC support both RDY/BUSY and DATA polling for write completion detection?

Yes, AT28C64E-12PC supports both methods. Pin 1 functions as an open-drain RDY/BUSY output that is actively pulled low during write operations and released high upon completion. Simultaneously, DATA polling is implemented on I/O7: reading the target location returns the complement of the written data until the write finishes, then true data appears. Both mechanisms are fully functional in the AT28C64E-12PC and documented in the Device Operation section. This dual-mode support gives designers flexibility in host controller implementation.

What is the purpose of the 32-byte identification memory in AT28C64E-12PC?

The AT28C64E-12PC includes 32 bytes of additional EEPROM space located at addresses 1FE0H–1FFFH, accessible only when A9 is raised to 12.0 V ± 0.5 V. This area is intended for device-specific data such as serial numbers, calibration coefficients, manufacturing date codes, or firmware version stamps. Unlike main array writes, this region uses the same 12 V programming method as chip erase but is byte-writable. It is electrically isolated from the primary 8K × 8 array and retains data independently.

Is AT28C64E-12PC pin-compatible with older AT28C64 variants?

Yes, AT28C64E-12PC maintains JEDEC-approved byte-wide pinout compatibility with all AT28C64 family members in the same 28-pin PDIP package-including AT28C64B-12PC and AT28C64-12PC. Pin functions (A0–A12, CE, OE, WE, I/O0–I/O7, RDY/BUSY, VCC, GND) match exactly. No PCB layout changes are required when upgrading from the B-version to the E-version. The only differences are internal: enhanced endurance (100K vs 10K cycles) and faster write timing (200 µs vs 1 ms), both transparent to the host interface.

What write protection mechanisms does AT28C64E-12PC implement?

AT28C64E-12PC implements three independent hardware write protection mechanisms: (1) VCC sense-write is inhibited if VCC drops below ~3.8 V; (2) Power-on delay-automatically blocks writes for 5 ms after VCC reaches 3.8 V; and (3) Logic-level inhibition-holding CE high, OE low, or WE high prevents any write initiation. These protections operate concurrently and require no software intervention. All are active during normal operation and are verified in the DC and AC characteristics tables of the datasheet. AT28C64E-12PC relies solely on these hardware safeguards-no software lock bits or command sequences are used.