My Inquiry
My Account
Microchip Technology AT28C64E-25JC
- Part No.:
- AT28C64E-25JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28C64E-25JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,287
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT28C64E-25JC from Atmel is a 64K-bit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 250 ns read access time, 200 µs fast byte write cycle, and CMOS/TTL-compatible I/O - used for nonvolatile configuration storage in industrial microcontroller systems requiring field-upgradable firmware parameters.
For engineers reviewing the AT28C64E-25JC datasheet, AT28C64E-25JC pinout, AT28C64E-25JC application, or AT28C64E-25JC equivalent, this page delivers verified timing specs, RDY/BUSY and DATA polling interface behavior, PLCC-32 package details, endurance (10⁵ cycles), and real-world use cases in embedded boot loaders and calibration data retention.
Technical Context
The AT28C64E-25JC operates as a drop-in parallel memory replacement for SRAM in read mode and implements self-timed internal write sequencing - latching address and data on WE/CE edges, then clearing and programming autonomously using an integrated control timer. It supports both RDY/BUSY level detection (open-drain pin 1) and DATA polling via I/O7 complement logic.
Its dual write protection mechanisms include VCC sense (inhibit below 3.8 V) and hardware inhibit via OE/CE/WE state logic. The device also provides CHIP CLEAR (12 V on A9 + WE pulse) and 32-byte user-identifiable memory at 1FE0H–1FFFH - all implemented in Atmel's nonvolatile floating-gate technology.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - sufficient for bootloader config tables or sensor calibration coefficients in resource-constrained MCU systems. |
| Read Access Time | 250 ns max - compatible with 4 MHz Z80, 8051, and 68K-based controllers without wait-state insertion. |
| Byte Write Time | 200 µs max - enables full 8K-byte rewrite in ≤1.6 seconds, critical for rapid field firmware updates. |
| Endurance | 100,000 write/erase cycles - validated for daily parameter logging over 27 years at one write per day. |
| Data Retention | 10 years at 85°C - ensures long-term reliability in industrial temperature environments without refresh. |
| Supply Voltage | 5 V ±10% - interoperable with legacy 5 V TTL/CMOS bus systems without level-shifting. |
| Standby Current | 100 µA typical - reduces power budget in battery-backed or low-power sleep modes. |
Pinout & Package
AT28C64E-25JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package with JEDEC MS-016AE footprint. Pin 1 is RDY/BUSY (open-drain); pins 1 and 17 are designated "Don't Connect" per PLCC variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; compatible with 8051/A68K address lines A0–A12. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; supports true read/write without external transceivers; I/O7 used for DATA polling. |
| CE | Chip Enable | Active-low chip select; enables memory access when low and OE low/WE high (read) or WE low (write). |
| OE | Output Enable | Active-low output control; places I/O bus in high-Z when high, preventing bus contention during shared-memory access. |
| WE | Write Enable | Active-low write strobe; initiates self-timed byte write on falling edge; latches data on rising edge. |
| RDY/BUSY | Open-Drain Status Output | Pulled low during write; released high at completion - allows wired-OR of multiple devices on single status line. |
| VCC, GND | Power Supply | 5 V supply and ground; decoupling capacitor required within 1 cm of pins 32 and 16 per layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Byte Write | Eliminates need for external timing circuitry - internal control timer manages erase-before-write and auto-termination. |
| DATA Polling Support | Enables software-driven write completion detection via I/O7 complement read - no extra hardware or interrupt lines needed. |
| RDY/BUSY Open-Drain Output | Allows direct connection to microcontroller INT pin or wired-OR with other EEPROMs for synchronized status monitoring. |
| VCC Sense Write Inhibit | Prevents corruption during brown-out by disabling writes if VCC drops below 3.8 V - no external supervisor IC required. |
| User-Accessible ID Memory | 32 bytes at 1FE0H–1FFFH support unique device serialization, calibration stamping, or firmware version tracking. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via 8051-compatible parallel bus during boot and runtime reconfiguration. Use Value: 100,000-cycle endurance ensures >10 years of daily parameter updates; 250 ns read time meets deterministic scan-cycle timing budgets. |
Use Scenario: Holding patient-specific calibration constants (e.g., sensor gain/offset) in portable ECG monitors subject to frequent recalibration. IC Role / Device Role / Timing Role: Dedicated calibration memory mapped into microcontroller address space; written only during service-mode calibration routines. Use Value: 10-year data retention at 85°C guarantees accuracy across device lifetime without battery backup or refresh logic. |
| Automotive Body Control Module Boot Parameters | Test Equipment Firmware Patch Storage |
|
Use Scenario: Storing CAN node IDs, wake-up mask settings, and lighting profiles in automotive BCMs operating across -40°C to +85°C. IC Role / Device Role / Timing Role: Parallel EEPROM interfaced to Renesas RL78 via standard address/data bus; accessed during cold start initialization. Use Value: Industrial temperature rating (-40°C to +85°C) and 5 V tolerance ensure robustness against automotive load-dump transients. |
Use Scenario: Hosting field-installable firmware patches for automated test equipment where full flash reprogramming is impractical. IC Role / Device Role / Timing Role: Hot-swappable configuration module enabling patch loading without system reboot or JTAG intervention. Use Value: 200 µs byte write enables sub-second patch application; RDY/BUSY signaling synchronizes host CPU without polling overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-25JC | Slower 1 ms byte write; 10K-cycle endurance; same pinout and voltage specs. | Lower-cost option for infrequently updated configurations where write speed and longevity are secondary. | Select when cost sensitivity outweighs field-upgrade speed requirements. |
| FM24C64-G | I²C interface (not parallel); 400 kHz max clock; 3.3 V only; no RDY/BUSY or DATA polling. | Requires MCU with I²C peripheral and software driver; unsuitable for direct SRAM-bus replacement. | Choose only if board redesign permits serial interface migration and 3.3 V system integration. |
Compared with AT28C64B-25JC, the AT28C64E-25JC delivers 5× faster writes and 10× higher endurance - essential for dynamic parameter logging. Versus FM24C64-G, it preserves legacy parallel bus architecture but requires dedicated address/data lines and higher supply voltage.
Availability
AT28C64E-25JC is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive body controllers, and test equipment requiring stable component supply with guaranteed long-term obsolescence management.
Supply support for AT28C64E-25JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs.
The AT28C64E-25JC belongs to Atmel's parallel EEPROM product line, designed specifically for seamless SRAM-drop-in replacement in legacy 8-bit and 16-bit embedded systems requiring field-upgradable nonvolatile storage.
FAQ
What is the maximum operating temperature range for the AT28C64E-25JC?
The AT28C64E-25JC is rated for industrial temperature operation from –40°C to +85°C. This specification is confirmed in the "DC and AC Operating Range" table of the official Atmel datasheet (Rev. 0001H), where the "-25" speed grade explicitly lists the industrial range. It is not qualified for extended military or automotive AEC-Q100 grades.
Does the AT28C64E-25JC support both RDY/BUSY and DATA polling for write completion detection?
Yes, the AT28C64E-25JC supports both methods. RDY/BUSY is provided on pin 1 as an open-drain output that goes low during write and releases high upon completion. DATA polling uses I/O7: reading the target location returns the complement of the written data until the write finishes, then returns true data. Both are documented in the "Device Operation" section of the datasheet.
What package type is used by the AT28C64E-25JC, and are all 32 leads functional?
The AT28C64E-25JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package (JEDEC MS-016AE). Pins 1 and 17 are designated "Don't Connect" (DC) per the Pin Configurations diagram - they must remain unconnected in PCB layout. All other pins serve defined functions including address, data, control, and power.
How does write protection work on the AT28C64E-25JC?
The AT28C64E-25JC implements three hardware write protection layers: (1) VCC sense - writes disabled if supply falls below ~3.8 V; (2) Power-on delay - automatic 5 ms lockout after VCC reaches threshold; (3) Signal-level inhibit - writes blocked unless CE is low, OE is high, and WE is low. These are detailed in the "WRITE PROTECTION" subsection of the datasheet.
Is the AT28C64E-25JC pin-compatible with the standard AT28C64-25JC?
Yes, the AT28C64E-25JC is fully pin-compatible with the AT28C64-25JC and AT28C64B-25JC. All share identical PLCC-32 pinout, voltage levels, timing interfaces, and control signal definitions. The "E" suffix denotes enhanced endurance (10⁵ vs. 10⁴ cycles) and faster write time (200 µs vs. 1 ms), with no physical or electrical interface changes.
AT28C64E-25JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 200µs
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28C64E-25JC FAQ
1.How can I place an order for AT28C64E-25JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64E-25JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64E-25JC reliable?
The price and inventory of AT28C64E-25JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64E-25JC is usually 5 days.
3.What payment methods are accepted for AT28C64E-25JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64E-25JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64E-25JC?
AT28C64E-25JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64E-25JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64E-25JC?
For technical support, including AT28C64E-25JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64E-25JC requirements.
6.How does Aetrix verify that AT28C64E-25JC is sourced from the original manufacturer or authorized distributors?
All AT28C64E-25JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64E-25JC meets industry standards.
7.What is the process for return or replacement of AT28C64E-25JC?
All AT28C64E-25JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64E-25JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64E-25JC part is unused and in its original packaging.
Return procedure for AT28C64E-25JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT28C64E-25JC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
