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Microchip Technology AT28C64X-25JC
- Part No.:
- AT28C64X-25JC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
AT28C64X-25JC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,194
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Product details
Overview
AT28C64X-25JC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with 250 ns read access time, self-timed byte write cycle, and CMOS/TTL-compatible I/O - used for nonvolatile configuration storage in industrial microcontroller systems requiring field-updatable firmware parameters.
For engineers reviewing the AT28C64X-25JC datasheet, AT28C64X-25JC pinout, AT28C64X-25JC application, or AT28C64X-25JC equivalent, key selection criteria include JEDEC-standard byte-wide pinout compatibility, RDY/BUSY signal absence in X-variant, 250 ns AC timing grade, industrial temperature range (-40°C to +85°C), and PLCC-32 packaging for high-reliability board-level reworkability.
Technical Context
The AT28C64X-25JC operates as a drop-in SRAM-compatible nonvolatile memory: reads require CE and OE low with WE high; writes initiate on falling WE (or CE) edge with internal latching of address and data. Its self-timed write cycle eliminates external timing control, using an internal timer and automatic pre-clear before programming.
Two end-of-write detection methods are supported: DATA Polling (I/O7 complement toggle) and RDY/BUSY output - though RDY/BUSY is unconnected (NC) on the AT28C64X variant per datasheet Pin Configurations section. Write protection relies on VCC sense (<3.8 V inhibition), 5 ms power-on delay, and triple-input inhibit logic (OE high, CE high, or WE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits) - supports full system configuration tables or boot parameter sets without external address decoding. |
| Read Access Time | 250 ns max - meets timing budgets for 4 MHz Z80 or 8 MHz 8051 bus cycles with standard wait-state logic. |
| Byte Write Time | 1 ms typical - enables reliable field updates without external timeout circuitry or software polling overhead beyond DATA Polling. |
| Supply Voltage | 5 V ± 10% - compatible with legacy 5 V logic rails and avoids level-shifting in industrial PLC backplanes. |
| Operating Temperature | -40°C to +85°C - qualified for deployment in motor drives, HVAC controllers, and factory automation equipment. |
| Standby Current | 100 µA max (CMOS) - reduces quiescent power in battery-backed or energy-sensitive embedded nodes. |
| Endurance | 10,000 write/erase cycles - sufficient for infrequent calibration storage or firmware revision tracking over 10+ years. |
| Data Retention | 10 years at +85°C - ensures long-term validity of stored calibration coefficients or security keys without refresh. |
Pinout & Package
AT28C64X-25JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016AE, with pin 1 index corner marked and pins 1 and 17 designated "Don't Connect" (DC). The package provides robust thermal performance and rework-friendly gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus supporting full 8K-word addressing; TTL/CMOS compatible thresholds ensure direct MCU interface. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel data path; supports true read/write without direction control lines - simplifies FPGA or ASIC glue logic. |
| CE | Chip Enable | Active-low chip select enabling memory mapping into microprocessor address space; dual-function with WE for write initiation. |
| OE | Output Enable | Active-low output gate controlling bus drivers; allows shared data bus operation with other peripherals without contention. |
| WE | Write Enable | Active-low write strobe; falling edge latches address and data internally, initiating self-timed byte programming sequence. |
| RDY/BUSY | Open-Drain Status Output | Not connected (NC) on AT28C64X variant - requires use of DATA Polling (I/O7) for write completion detection. |
| VCC | Power Supply | +5 V ±10% supply input; decoupling capacitor placement near pin 32 critical for stable write timing. |
| GND | Ground Reference | Signal and power ground return; pin 16 in PLCC layout - placed adjacent to VCC for low-inductance bypassing. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Byte Write Cycle | Eliminates need for external write pulse generators or timing state machines - reduces BOM count and PCB area in resource-constrained designs. |
| DATA Polling Support | Enables deterministic write completion detection via I/O7 complement toggle - no additional GPIO or interrupt line required. |
| JEDEC Byte-wide Pinout | Ensures mechanical and electrical compatibility with legacy SRAM sockets and memory controllers designed for 28-pin DIP/TSOP footprints. |
| VCC Sense Write Inhibit | Prevents corruption during brown-out or power ramp-up by disabling writes below 3.8 V - critical for fail-safe firmware update sequences. |
| Industrial Temperature Range | Validated operation from -40°C to +85°C - supports deployment in uncontrolled environments like outdoor metering or transportation electronics. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Parameter Retention |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning constants, and alarm thresholds in programmable logic controllers deployed in factory floors. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed via 8051 or ARM Cortex-M3 parallel bus during boot and runtime parameter updates. Use Value: Enables field recalibration without firmware reflashing; 10-year data retention guarantees parameter integrity across maintenance cycles. |
Use Scenario: Holding sensor offset/gain coefficients and regulatory compliance flags in portable ultrasound or infusion pump controllers. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter vault with VCC-sense write protection preventing accidental overwrite during battery swaps. Use Value: Meets IEC 62304 Class C software requirements for persistent data integrity; 10,000-cycle endurance supports lifetime device recalibration. |
| Automotive ECU Bootloader Settings | Telecom Base Station Firmware Patch Storage |
Use Scenario: Storing bootloader jump vectors, secure boot keys, and CAN node ID assignments in engine control units operating under under-hood thermal stress. IC Role / Device Role / Timing Role: High-reliability configuration store interfaced directly to MPC56xx or S32K1xx parallel memory bus with no glue logic. Use Value: Industrial-grade temperature qualification (-40°C to +85°C) ensures functionality during cold cranking and hot soak conditions. |
Use Scenario: Caching firmware patch binaries and version metadata in remote radio head controllers requiring zero-downtime updates. IC Role / Device Role / Timing Role: Parallel-accessible nonvolatile scratchpad memory mapped into DSP or ARM9 memory space for rapid patch loading. Use Value: 250 ns read access enables sub-microsecond patch validation; 1 ms write time aligns with telecom-defined update windows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-25JC | Same 64 Kbit capacity, 250 ns speed, PLCC-32 package; differs in internal error correction architecture and enhanced data retention test methodology. | Qualified for extended life-cycle programs where >10-year data retention at +85°C is contractually mandated. | Select when higher data integrity assurance is required; not drop-in due to different endurance characterization (100K vs. 10K cycles). |
| MX28LV640E-25P | 64 Kbit parallel EEPROM, 250 ns access, PDIP-28 package; lacks RDY/BUSY pin and uses different write inhibit voltage thresholds (VCC only, no 12 V A9 support). | Suitable for cost-sensitive consumer electronics where PLCC reworkability is unnecessary and 12 V device identification is unused. | Select for legacy DIP-based designs; requires PCB footprint change and verification of write-protection behavior under marginal VCC. |
Compared with AT28C64X-25JC, AT28C64B-25JC offers improved data retention certification but requires design revalidation, while MX28LV640E-25P trades PLCC reworkability and 12 V device ID capability for lower unit cost in through-hole assembly.
Availability
AT28C64X-25JC is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive ECUs, and telecom base stations requiring stable component supply across multi-year production lifecycles.
Supply support for AT28C64X-25JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for industrial and automotive markets.
The AT28C64X series was designed as a pin-compatible, SRAM-transparent parallel EEPROM family targeting legacy 8-bit and 16-bit microprocessor systems needing field-updatable nonvolatile storage without redesigning memory interfaces.
FAQ
What is the maximum read access time specified for the AT28C64X-25JC?
The AT28C64X-25JC has a maximum read access time of 250 ns, as defined in the AC Read Characteristics table for the -25 speed grade. This value is guaranteed across the full industrial temperature range (-40°C to +85°C) and 5 V ±10% supply, enabling direct interface with microprocessors such as the 80C51 or Z80 running at up to 4 MHz without wait states. The AT28C64X-25JC achieves this timing using Atmel's optimized CMOS EEPROM process.
Does the AT28C64X-25JC support the RDY/BUSY signal for write completion detection?
No, the AT28C64X-25JC does not support the RDY/BUSY signal: pin 1 is designated "Don't Connect" (DC) per the LCC/PLCC pin configuration diagram. Write completion must be detected exclusively via DATA Polling on I/O7, which toggles to the complement of written data during programming and returns to true data upon completion. This behavior is fully documented in the Device Operation section of the AT28C64X-25JC datasheet.
What is the endurance rating of the AT28C64X-25JC, and how is it verified?
The AT28C64X-25JC is rated for 10,000 write/erase cycles, as confirmed in the Features section and DC Characteristics table. This endurance is validated per JEDEC standard JESD22-A117 using accelerated life testing at elevated temperature and voltage stress. The AT28C64X-25JC does not include the "E" suffix (e.g., AT28C64E), which denotes the 100,000-cycle variant; endurance is fixed per ordering code and cannot be upgraded via firmware or configuration.
Can the AT28C64X-25JC be used as a direct replacement for standard SRAM in existing designs?
Yes, the AT28C64X-25JC supports SRAM-like read access with identical CE/OE/WE control timing, allowing drop-in replacement in many cases - but write behavior differs fundamentally. Unlike SRAM, the AT28C64X-25JC requires write cycle detection (via DATA Polling) and has 1 ms latency per byte write. Designs must implement polling or software delays; unmodified SRAM write routines will corrupt data. The AT28C64X-25JC retains data without power, eliminating battery backup requirements.
What package type and lead finish does the AT28C64X-25JC use?
The AT28C64X-25JC uses a 32-lead Plastic J-Leaded Chip Carrier (PLCC) package per JEDEC MS-016AE, with matte tin (Sn) lead finish compliant with RoHS Directive 2011/65/EU. The package features gull-wing leads, 1.27 mm pitch, and a body size of 13.7 mm × 11.9 mm. Pin 1 is marked by a corner chamfer and dot; pins 1 and 17 are explicitly designated "Don't Connect" in the AT28C64X-25JC datasheet.
AT28C64X-25JC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
AT28C64X-25JC FAQ
1.How can I place an order for AT28C64X-25JC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64X-25JC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64X-25JC reliable?
The price and inventory of AT28C64X-25JC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64X-25JC is usually 5 days.
3.What payment methods are accepted for AT28C64X-25JC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64X-25JC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT28C64X-25JC?
AT28C64X-25JC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64X-25JC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64X-25JC?
For technical support, including AT28C64X-25JC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64X-25JC requirements.
6.How does Aetrix verify that AT28C64X-25JC is sourced from the original manufacturer or authorized distributors?
All AT28C64X-25JC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64X-25JC meets industry standards.
7.What is the process for return or replacement of AT28C64X-25JC?
All AT28C64X-25JC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64X-25JC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64X-25JC part is unused and in its original packaging.
Return procedure for AT28C64X-25JC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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