Microchip Technology AT28C64X-25PC
- Part No.:
- AT28C64X-25PC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 28-DIP (0.600", 15.24mm)
- Datasheet:
-
AT28C64X-25PC.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 28DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT28C64X-25PC from Atmel is a 64 Kbit (8K × 8) parallel EEPROM with JEDEC-standard byte-wide pinout, 250 ns read access time, 1 ms fast byte write cycle, and CMOS/TTL-compatible I/O. It operates at 5V ±10%, supports commercial temperature range (0°C to 70°C), and delivers 30 mA active current with 100 µA standby current for embedded microcontroller systems requiring nonvolatile configuration storage.
For engineers reviewing the AT28C64X-25PC datasheet, AT28C64X-25PC pinout, AT28C64X-25PC application, or AT28C64X-25PC equivalent, key selection criteria include its self-timed write architecture, RDY/BUSY signal omission (pin 1 NC), DATA polling support, JEDEC-compliant PDIP-28 package, and compatibility with 8-bit microprocessor buses without external timing logic.
Technical Context
The AT28C64X-25PC implements a self-timed byte write cycle with internal address/data latches and automatic clear-before-write logic, eliminating need for external write timing control. Its READY/BUSY output is omitted (NC on pin 1), relying exclusively on DATA polling via I/O7 for write completion detection.
It functions as a drop-in SRAM replacement for reads and writes-CE/OE/WE control enables direct microprocessor interfacing. The device uses Atmel's nonvolatile EEPROM technology with built-in error correction for 10⁴ write endurance and 10-year data retention, and includes 32 bytes of user-accessible identification memory at addresses 1FE0H–1FFFH.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 Kbit (8,192 × 8 bits); provides full byte-addressable nonvolatile storage for firmware patches or calibration tables. |
| Read Access Time | 250 ns max; meets timing requirements of 4 MHz Z80, 8051, and 68000-based systems without wait states. |
| Byte Write Time | 1 ms typical; enables reliable in-system programming with minimal CPU intervention during write cycles. |
| Supply Voltage | 5 V ±10%; compatible with standard TTL/CMOS logic rails and legacy industrial power supplies. |
| Operating Temperature | 0°C to 70°C; validated for commercial-grade instrumentation, POS terminals, and office equipment. |
| Standby Current | 100 µA max; reduces system-level power consumption during idle periods in battery-backed applications. |
| Endurance | 10,000 write/erase cycles; sufficient for infrequent configuration updates over 10+ years of field operation. |
Pinout & Package
AT28C64X-25PC is packaged in a 28-lead, 0.600" wide plastic DIP (PDIP-28), JEDEC MS-011 AB compliant, with through-hole mounting and 2.54 mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus accepting 0000H–1FFFH for full 8K-word addressing. |
| I/O0–I/O7 | Bidirectional Data Bus | 8-bit parallel interface supporting read/write data transfer synchronized to WE/CE edges. |
| CE | Chip Enable | Active-low chip select; enables memory access when low and OE is low (read) or WE is low (write). |
| OE | Output Enable | Active-low output control; places I/O pins in high-impedance state when high to prevent bus contention. |
| WE | Write Enable | Active-low write strobe; initiates self-timed byte write on falling edge with data latched on rising edge. |
| RDY/BUSY | Open-Drain Status Output | No-connect (NC) on AT28C64X variant; write completion must be detected via DATA polling only. |
| VCC | Power Supply | +5 V supply input; internal VCC sense disables writes if voltage drops below 3.8 V. |
| GND | Ground Reference | Signal and power ground reference for all inputs, outputs, and internal circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed byte write | Eliminates external timing circuitry; internal control timer manages erase-and-program sequence automatically. |
| DATA polling (I/O7) | Enables software-driven write completion detection without hardware status lines or interrupts. |
| Write protection logic | VCC sense, power-on delay, and CE/OE/WE gating prevent accidental writes during power transitions or noise events. |
| User identification memory | 32-byte reserved block (1FE0H–1FFFH) accessible via A9 = 12 V for serialization or firmware version tracking. |
| JEDEC byte-wide pinout | Ensures PCB layout compatibility with legacy SRAMs and other parallel EEPROMs across multiple vendors. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing sensor calibration coefficients and operational thresholds in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing byte-addressable, field-updatable parameter storage with guaranteed 10-year retention. Use Value: Enables recalibration without firmware reflash; 10⁴ endurance supports quarterly maintenance cycles over 10+ years. |
Use Scenario: Retaining patient-specific therapy parameters and device serial traceability in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure, low-power configuration memory accessed during boot and runtime by ARM Cortex-M3 host MCU. Use Value: 100 µA standby current extends battery life; 5V tolerance simplifies integration with existing 5V analog front-end power domains. |
| Point-of-Sale Terminal Firmware Patching | Telecom Line Card Bootloader Parameters |
Use Scenario: Hosting minor firmware patches and localization strings in retail POS terminals where full flash reprogramming is impractical. IC Role / Device Role / Timing Role: Parallel EEPROM acting as auxiliary code/data store mapped into microcontroller address space alongside main ROM. Use Value: 250 ns read speed allows zero-wait-state execution; JEDEC pinout permits reuse of existing PCB footprint from SRAM-based designs. |
Use Scenario: Storing board-specific initialization values (e.g., clock dividers, PHY settings) on telecom line cards requiring hot-swap capability. IC Role / Device Role / Timing Role: Configuration memory accessed early in boot sequence by FPGA or DSP before main application loads. Use Value: RDY/BUSY omission simplifies routing; DATA polling ensures deterministic timing even under variable bus loading conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar parallel EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-25PC | Enhanced revision with improved data retention (20 years) and tighter tACC spec (250 ns guaranteed vs. characterized); same pinout and timing. | Preferred for new designs requiring extended lifecycle compliance; identical drop-in replacement for AT28C64X-25PC. | Select AT28C64B-25PC for long-term production programs where 20-year data retention is mandated. |
| MX28LV640C-25PC | Macronix 64 Kbit parallel EEPROM with 250 ns access, but requires 12 V for chip erase and lacks built-in VCC sense write inhibit. | Suitable for cost-sensitive applications where external 12 V generation is acceptable and write protection is managed externally. | Choose MX28LV640C-25PC only if board already provides 12 V and design can accommodate additional voltage rail management. |
Compared with AT28C64X-25PC, AT28C64B-25PC offers longer data retention and tighter AC specs without layout changes, while MX28LV640C-25PC trades integrated write safety for lower unit cost but adds system-level voltage complexity.
Availability
AT28C64X-25PC is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, point-of-sale terminals, and telecom infrastructure requiring stable component supply across multi-year production cycles.
Supply support for AT28C64X-25PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a fabless semiconductor company specializing in microcontrollers, nonvolatile memory, and secure authentication ICs for embedded applications.
The AT28C64X series was designed as a pin-compatible, low-power parallel EEPROM family targeting legacy 8-bit microprocessor systems needing reliable, easy-to-integrate nonvolatile storage without external timing components.
FAQ
What is the maximum read access time specified for the AT28C64X-25PC?
The AT28C64X-25PC has a maximum read access time (tACC) of 250 ns, as indicated by the "-25" suffix in its part number. This value is guaranteed across the commercial temperature range (0°C to 70°C) and applies to all package variants including the PDIP-28 used in AT28C64X-25PC. The specification ensures compatibility with 4 MHz bus systems without wait-state insertion.
Does the AT28C64X-25PC include a functional RDY/BUSY output pin?
No, the AT28C64X-25PC does not implement the RDY/BUSY function. Pin 1 is designated as "NC" (No Connect) per the datasheet, distinguishing it from the base AT28C64 variant. Write completion must be detected using DATA polling on I/O7, where the complement of written data appears until the internal self-timed cycle completes.
What is the write endurance rating of the AT28C64X-25PC?
The AT28C64X-25PC is rated for 10,000 (10⁴) write/erase cycles, as confirmed in the "Features" section and DC characteristics table. This endurance level is sufficient for applications involving infrequent updates-such as quarterly calibration or annual firmware patching-over a minimum 10-year service life under typical operating conditions.
Can the AT28C64X-25PC operate with a 3.3 V supply?
No, the AT28C64X-25PC requires a 5 V ±10% supply (4.5 V to 5.5 V) and is not rated for 3.3 V operation. Its input thresholds (VIL = 0.8 V, VIH = 2.0 V) and internal VCC sense circuitry (which inhibits writes below ~3.8 V) are optimized for 5 V TTL/CMOS logic families. Using 3.3 V will result in unreliable reads, failed writes, or undefined behavior.
How is device identification implemented in the AT28C64X-25PC?
The AT28C64X-25PC includes 32 bytes of dedicated identification memory at addresses 1FE0H–1FFFH. To access this region, A9 must be raised to 12.0 V ±0.5 V while applying standard CE/OE/WE control signals. This allows OEMs to store unique serial numbers, manufacturing dates, or firmware version stamps without consuming main array space.
AT28C64X-25PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 28-DIP (0.600", 15.24mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 250 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 28-PDIP
AT28C64X-25PC FAQ
1.How can I place an order for AT28C64X-25PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT28C64X-25PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT28C64X-25PC reliable?
The price and inventory of AT28C64X-25PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT28C64X-25PC is usually 5 days.
3.What payment methods are accepted for AT28C64X-25PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT28C64X-25PC transactions.
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4.How is shipping managed for AT28C64X-25PC?
AT28C64X-25PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT28C64X-25PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT28C64X-25PC?
For technical support, including AT28C64X-25PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT28C64X-25PC requirements.
6.How does Aetrix verify that AT28C64X-25PC is sourced from the original manufacturer or authorized distributors?
All AT28C64X-25PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT28C64X-25PC meets industry standards.
7.What is the process for return or replacement of AT28C64X-25PC?
All AT28C64X-25PC units undergo pre-shipment inspection (PSI). If there is an issue with AT28C64X-25PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT28C64X-25PC part is unused and in its original packaging.
Return procedure for AT28C64X-25PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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